Patents by Inventor Yun-Tai SHIH
Yun-Tai SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11721662Abstract: A method of aligning two wafers during a bonding process includes aligning a first wafer having a plurality of alignment markings with a second wafer having a plurality of alignment markings. The method further includes placing a plurality of flags between the first wafer and the second wafer. The method further includes detecting movement of the plurality of flags with respect to the first wafer and the second wafer using at least one sensor. The method further includes determining whether the wafers remain aligned within an alignment tolerance based on the detected movement of the plurality of flags relative to the first wafer and the second wafer.Type: GrantFiled: November 4, 2020Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai Shih, Ching-Hou Su, Chyi-Tsong Ni, I-Shi Wang, Jeng-Hao Lin, Kuan-Ming Pan, Jui-Mu Cho, Wun-Kai Tsai
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Publication number: 20210050324Abstract: A method of aligning two wafers during a bonding process includes aligning a first wafer having a plurality of alignment markings with a second wafer having a plurality of alignment markings. The method further includes placing a plurality of flags between the first wafer and the second wafer. The method further includes detecting movement of the plurality of flags with respect to the first wafer and the second wafer using at least one sensor. The method further includes determining whether the wafers remain aligned within an alignment tolerance based on the detected movement of the plurality of flags relative to the first wafer and the second wafer.Type: ApplicationFiled: November 4, 2020Publication date: February 18, 2021Inventors: Yun-Tai SHIH, Ching-Hou SU, Chyi-Tsong NI, I-Shi WANG, Jeng-Hao LIN, Kuan-Ming PAN, Jui-Mu CHO, Wun-Kai TSAI
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Patent number: 10847490Abstract: An apparatus includes an alignment module configured to align a first wafer and a second wafer based on alignment markers on the first wafer and corresponding alignment markers on the second wafer. The apparatus further includes a flag placement module configured to insert a plurality of flags between the first wafer and the second wafer, a flag-out mechanism configured to simultaneously move the plurality of flags to a flag-out position, and a controller configured to determine whether the wafers remain aligned within an alignment tolerance based on an amount of time for each flag of the plurality of flags to reach the flag-out position.Type: GrantFiled: August 21, 2019Date of Patent: November 24, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai Shih, Kuan-Ming Pan, Jeng-Hao Lin, I-Shi Wang, Jui-Mu Cho, Ching-Hou Su, Chyi-Tsong Ni, Wun-Kai Tsai
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Publication number: 20190378813Abstract: An apparatus includes an alignment module configured to align a first wafer and a second wafer based on alignment markers on the first wafer and corresponding alignment markers on the second wafer. The apparatus further includes a flag placement module configured to insert a plurality of flags between the first wafer and the second wafer, a flag-out mechanism configured to simultaneously move the plurality of flags to a flag-out position, and a controller configured to determine whether the wafers remain aligned within an alignment tolerance based on an amount of time for each flag of the plurality of flags to reach the flag-out position.Type: ApplicationFiled: August 21, 2019Publication date: December 12, 2019Inventors: Yun-Tai SHIH, Kuan-Ming PAN, Jeng-Hao LIN, I-Shi WANG, Jui-Mu CHO, Ching-Hou SU, Chyi-Tsong NI, Wun-Kai TSAI
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Patent number: 10396054Abstract: An apparatus includes a bonding system configured to bond at least two wafers. The bonding system has a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers. The apparatus also includes sensors configured to detect data related to a flag-out condition of the flags of the plurality of flag. The apparatus further includes at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers.Type: GrantFiled: August 6, 2015Date of Patent: August 27, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai Shih, Kuan-Ming Pan, Jeng-Hao Lin, I-Shi Wang, Jui-Mu Cho, Ching-Hou Su, Chyi-Tsong Ni, Wun-Kai Tsai
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Publication number: 20150340337Abstract: An apparatus includes a bonding system configured to bond at least two wafers. The bonding system has a flag-out mechanism configured to remove a plurality of flags from an area between the at least two wafers. The apparatus also includes sensors configured to detect data related to a flag-out condition of the flags of the plurality of flag. The apparatus further includes at least one processor configured to receive inputs from the sensors, to calculate at least one value related to flag-out timing, and to drive a display indicating an alignment of the at least two wafers.Type: ApplicationFiled: August 6, 2015Publication date: November 26, 2015Inventors: Yun-Tai SHIH, Kuan-Ming PAN, Jeng-Hao LIN, I-Shi WANG, Jui-Mu CHO, Ching-Hou SU, Chyi-Tsong NI, Wun-Kai TSAI
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Patent number: 9123754Abstract: An apparatus is disclosed for detecting flag velocity during a eutectic process for bonding two wafers. The apparatus includes a plurality of sensors for detecting a time and/or velocity of a plurality of flags within a flag-out mechanism. The apparatus also includes one or more displays displaying time durations associated with the movement of the flags during the bonding process. Also disclosed is a method of aligning wafers in a eutectic bonding process. The method includes determining one or more time durations associated with the movement of the flags in the plurality of flags. The method also includes determining if a misalignment has occurred based on the one or more time durations associated with the movement of the flags.Type: GrantFiled: October 6, 2011Date of Patent: September 1, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai Shih, Kuan-Ming Pan, Jeng-Hao Lin, I-Shi Wang, Jui-Mu Cho, Ching-Hou Su, Chyi-Tsong Ni, Wun-Kai Tsai
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Publication number: 20130086786Abstract: An apparatus is disclosed for detecting flag velocity during a eutectic process for bonding two wafers. The apparatus includes a plurality of sensors for detecting a time and/or velocity of a plurality of flags within a flag-out mechanism. The apparatus also includes one or more displays displaying time durations associated with the movement of the flags during the bonding process. Also disclosed is a method of aligning wafers in a eutectic bonding process. The method includes determining one or more time durations associated with the movement of the flags in the plurality of flags. The method also includes determining if a misalignment has occurred based on the one or more time durations associated with the movement of the flags.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Tai SHIH, Kuan-Ming PAN, Jeng-Hao LIN, I-Shi WANG, Jui-Mu CHO, Ching-Hou SU, Chyi-Tsong NI, Wun-Kai TSAI