Patents by Inventor Yun-Tzuo Lai
Yun-Tzuo Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11816338Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: GrantFiled: September 28, 2022Date of Patent: November 14, 2023Assignee: Western Digital Technologies, Inc.Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
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Patent number: 11645217Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.Type: GrantFiled: May 25, 2021Date of Patent: May 9, 2023Assignee: Western Digital Technologies, Inc.Inventors: Scott Jinn, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
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Patent number: 11630609Abstract: Systems and methods are disclosed for scheduling access commands for a data storage device. A data storage device determines a layout of a plurality of non-volatile memory arrays. The data storage device also determine completed access statistics and pending access statistics for a first set of the plurality of non-volatile memory arrays during a monitoring period. The data storage device further generates a schedule based on the layout of the plurality of non-volatile memory arrays, the completed access statistics, and the pending access statistics and executes access commands based on schedule.Type: GrantFiled: July 23, 2020Date of Patent: April 18, 2023Assignee: Western Digital Technologies, Inc.Inventors: Haining Liu, YungLi Ji, Yun-Tzuo Lai, Ming-Yu Tai
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Patent number: 11630720Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: GrantFiled: June 24, 2021Date of Patent: April 18, 2023Assignee: Western Digital Technologies, Inc.Inventors: Parvaneh Alavi, Kai-Lung Cheng, Yun-Tzuo Lai, Haining Liu
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Publication number: 20230017605Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: ApplicationFiled: September 28, 2022Publication date: January 19, 2023Applicant: Western Digital Technologies, Inc.Inventors: Yun-Tzuo LAI, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 11487437Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: GrantFiled: April 5, 2021Date of Patent: November 1, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
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Patent number: 11474709Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: January 20, 2021Date of Patent: October 18, 2022Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 11435908Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.Type: GrantFiled: October 30, 2020Date of Patent: September 6, 2022Assignee: Western Digital Technologies, Inc.Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
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Publication number: 20210318927Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: Parvaneh ALAVI, Kai-Lung CHENG, Yun-Tzuo LAI, Haining LIU
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Publication number: 20210279196Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Inventors: Scott JINN, Yun-Tzuo LAI, Haining LIU, Yuriy PAVLENKO
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Patent number: 11086712Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: GrantFiled: November 22, 2019Date of Patent: August 10, 2021Assignee: Western Digital Technologies, Inc.Inventors: Parvaneh Alavi, Kai-Lung Cheng, Yun-Tzuo Lai, Haining Liu
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Publication number: 20210223965Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Yun-Tzuo LAI, Haining LIU, Subhash Balakrishna PILLAI
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Patent number: 11061842Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.Type: GrantFiled: March 23, 2020Date of Patent: July 13, 2021Assignee: Western Digital Technologies, Inc.Inventors: Scott Jinn, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
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Patent number: 11048589Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: GrantFiled: April 17, 2019Date of Patent: June 29, 2021Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20210141542Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: 10990296Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.Type: GrantFiled: November 25, 2019Date of Patent: April 27, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES. INC.Inventors: Yun-Tzuo Lai, Haining Liu, Subhash Balakrishna Pillai
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Publication number: 20210048954Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.Type: ApplicationFiled: October 30, 2020Publication date: February 18, 2021Inventors: YungLi JI, Yun-Tzuo LAI, Haining LIU, Yuriy PAVLENKO
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Patent number: 10901632Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: July 26, 2019Date of Patent: January 26, 2021Assignee: WESTERN DITIGAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 10846000Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.Type: GrantFiled: June 27, 2019Date of Patent: November 24, 2020Assignee: Western Digital Technologies, Inc.Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
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Publication number: 20200356312Abstract: Systems and methods are disclosed for scheduling access commands for a data storage device. A data storage device determines a layout of a plurality of non-volatile memory arrays. The data storage device also determine completed access statistics and pending access statistics for a first set of the plurality of non-volatile memory arrays during a monitoring period. The data storage device further generates a schedule based on the layout of the plurality of non-volatile memory arrays, the completed access statistics, and the pending access statistics and executes access commands based on schedule.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Inventors: Haining LIU, YungLi JI, Yun-Tzuo LAI, Ming-Yu TAI