Patents by Inventor Yun-Xiang LIN
Yun-Xiang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230306181Abstract: A method performed by a computer system includes: searching leakage current values of associated with cell abutment cases which are associated with terminal types of abutted cells of a semiconductor device; determining leakage probabilities according to the cell abutment cases; calculating expected boundary leakages between the abutted cells based on the leakage probabilities and the leakage current values; and generating a layout of the semiconductor device according to the expected boundary leakages. Two of the leakage probabilities correspond to two of the cell abutment cases, respectively, and the two of the leakage probabilities are different from each other when the two of the cell abutment cases are different from each other.Type: ApplicationFiled: June 1, 2023Publication date: September 28, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hua LIU, Yun-Xiang LIN, Yuan-Te HOU, Chung-Hsing WANG
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Patent number: 11720738Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.Type: GrantFiled: May 7, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou, Chung-Hsing Wang
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Patent number: 11714949Abstract: A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.Type: GrantFiled: May 7, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou, Chung-Hsing Wang
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Publication number: 20210264093Abstract: A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hua LIU, Yun-Xiang LIN, Yuan-Te HOU, Chung-Hsing WANG
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Publication number: 20210264092Abstract: A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hua LIU, Yun-Xiang LIN, Yuan-Te HOU, Chung-Hsing WANG
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Patent number: 11030381Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.Type: GrantFiled: September 27, 2019Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hua Liu, Yun-Xiang Lin, Yuan-Te Hou, Chung-Hsing Wang
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Publication number: 20200226229Abstract: A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.Type: ApplicationFiled: September 27, 2019Publication date: July 16, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Hua LIU, Yun-Xiang LIN, Yuan-Te HOU, Chung-Hsing WANG
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Patent number: 10331838Abstract: A layout method is disclosed that includes: placing function cells in a layout, corresponding to at least one design file, of an integrated circuit; and inserting at least one fill cell that is configured without cut pattern to fill at least one empty region between the function cells each comprising at least one cut pattern on at least one edge abutting the at least one empty region.Type: GrantFiled: July 26, 2017Date of Patent: June 25, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chan Yang, Hui-Zhong Zhuang, Ting-Wei Chiang, Yun-Xiang Lin, Tien-Yu Kuo, Shu-Yi Ying
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Publication number: 20180165399Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.Type: ApplicationFiled: July 26, 2017Publication date: June 14, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chan YANG, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Yun-Xiang LIN, Tien-Yu KUO, Shu-Yi YING