Abstract: The portion of TDMA frames otherwise containing the sync word is eliminated for one or more data frames at the end of a TDMA data burst to provided added bandwidth for data payload or for a reduced bandwidth. Once a communication channel has been established and is in steady state mode (after receipt of one or more frames), the sync word is eliminated from the remaining frame structure. Drift of a local clock with respect to an incoming data stream is monitored using an oversampled or multiplied master clock to provide suitable resolution to determine an approximate position of an active edge of the master clock with respect to a bit or symbol being clocked. Any drift from center results in an adjustment of the local master clock. In a preferred embodiment, the drift is measured in a last bit or symbol of a received TDMA burst, and the master clock is adjusted to re-center the local master clock with respect to that last bit.

Abstract: A timing recovery circuit and method which determines whether a sample point in a generated bit sequence is early or late based on binary logic which is already available used in generating a bit sequence by comparing energy magnitudes of adjacent bits. The waveform of an input symbol is correlated against reference waveforms. When the incoming waveform does not perfectly match a reference waveform, symbol energy less than maximum is output indicating that the timing of the sampling points is either early or late. Symbol energy magnitudes between adjacent bits are then compared. Using the bit pattern of the generated bit sequence and the results of comparisons of energy magnitudes of adjacent bits, it is determined whether the timing of the sampling points is early or whether it is late.

Abstract: The portion of TDMA frames otherwise containing the sync word is eliminated for one or more data frames at the end of a TDMA data burst to provided added bandwidth for data payload or for a reduced bandwidth. Once a communication channel has been established and is in steady state mode (after receipt of one or more frames), the sync word is eliminated from the remaining frame structure. Drift of a local clock with respect to an incoming data stream is monitored using an oversampled or multiplied master clock to provide suitable resolution to determine an approximate position of an active edge of the master clock with respect to a bit or symbol being clocked. Any drift from center results in an adjustment of the local master clock. In a preferred embodiment, the drift is measured in a last bit or symbol of a received TDMA burst, and the master clock is adjusted to re-center the local master clock with respect to that last bit.

Abstract: A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. The undesirable portion of the upconverted signal may be suppressed using I/Q image rejection, and/or an appropriate bandpass filter may be used. A band limited, hard limited signal at the high IF is presented to the 1-bit precision demodulator as a receive IF signal, which is treated as a 1-bit quantization of the signal. The receive IF signal is digitally down-converted to a low IF signal to produce an alias signal at the low IF frequency.