Patents by Inventor Yun XIE

Yun XIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240353318
    Abstract: Methods and systems for inspecting a photomask are provided. One system includes an illumination subsystem configured to direct light to the photomask. The system also includes a pupil filter positioned in a path of only the light from the photomask and configured for controlling a polarization of the light in the path by mixing four elements in a Jones matrix for the photomask in a coherent manner. In addition, the system includes a detector configured for detecting the light from the pupil filter and generating output responsive to the detected light. The system further includes a computer subsystem configured for detecting defects on the photomask based on the output.
    Type: Application
    Filed: January 22, 2024
    Publication date: October 24, 2024
    Inventors: Yun Xie, Rui-Fang Shi, Xin Ye, Heng Zhang
  • Patent number: 11973925
    Abstract: The present disclosure relates to the field of visual images. A stereoscopic display screen includes: an optical component, configured to provide an optical signal of which the light intensity is lower than the light intensity of video information; a transparent display component, configured to display the video information; and a space imaging frame component, configured to form a hollow enclosed cavity which is visible from the front and has a rear end sealed by the transparent display component. A foreground stage imaging area is formed in an internal region of the space imaging frame component, the space imaging frame component forms, at a position opposite the optical component, a virtual space imaging frame component which takes an axial plane of the transparent display component as a mirror symmetrical plane, and a virtual background stage imaging area is formed in the virtual space imaging frame component.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: April 30, 2024
    Inventor: Yun Xie
  • Publication number: 20230418167
    Abstract: A system and method for cleaning an optical element of an EUV optical system is disclosed. The system and method may include receiving design data of one or more samples. The system and method may include simulating a plurality of irradiance distributions at a plane of an EUV optical sub-system based on the design data and one or more parameters. The system and method may include aggregating the plurality of irradiance distributions to generate an aggregated irradiance distribution. The system and method may include determining a predicted contaminate distribution based on both the aggregated irradiance distribution and a contaminate growth rate. The system and method may include determining a cleaning recipe for the one or more optical elements based on the predicted contaminate distribution.
    Type: Application
    Filed: September 13, 2022
    Publication date: December 28, 2023
    Inventors: Yun Xie, Rui-Fang Shi, Shannon Hill
  • Publication number: 20230304907
    Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for foam generation, and to apparatus and methods for evaluation of foam systems. In an embodiment, a method of analyzing foam properties includes delivering a foaming composition and a gas to a housing at a pressure of 500 psi to 6,000 psi and a temperature of 35° C. to 150° C., the housing containing an unconsolidated porous media. The method further includes flowing the foaming composition and the gas through the housing, and forming a foam by an interaction of the foaming composition, the gas, and the unconsolidated porous media. The method further includes directing the foam from the housing to a visualization chamber, the visualization chamber in fluid communication with the housing, and measuring a foam characteristic via the visualization chamber. The characteristic may include foam half-life, pressure drop through the unconsolidated media, and/or apparent viscosity of the foam.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 28, 2023
    Inventors: Mohammad PIRI, Yun XIE, Keerti Vardhan SHARMA, Van Si LE, Magda Ibrahim YOUSSIF, Alvinda Sri HANAMERTANI, Omar ELKHATIB, Kaustubh Shriram RANE
  • Patent number: 11599654
    Abstract: A method and an apparatus for authority control, a computer device, and a storage medium, and relates to the field of the Internet technologies. The method includes: acquiring a configuration file according to a business scenario when a container is initialized, wherein the configuration file is managed outside the container; validating the configuration file in the container; receiving a user instruction; and identifying a type of the user instruction when the user instruction is an executable instruction. The method further including acquiring script content of a script file when the type of the user instruction indicates that the user instruction is the script file, wherein the script content includes at least one command statement; and performing a validity check on the at least one command statement based on the configuration file.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: March 7, 2023
    Assignees: ENVISION DIGITAL INTERNATIONAL PTE. LTD., SHANGHAI ENVISION DIGITAL CO., LTD.
    Inventor: Yun Xie
  • Publication number: 20230036357
    Abstract: A method and an apparatus for authority control, a computer device, and a storage medium, and relates to the field of the Internet technologies. The method includes: acquiring a configuration file according to a business scenario when a container is initialized, wherein the configuration file is managed outside the container; validating the configuration file in the container; receiving a user instruction; and identifying a type of the user instruction when the user instruction is an executable instruction. The method further including acquiring script content of a script file when the type of the user instruction indicates that the user instruction is the script file, wherein the script content includes at least one command statement; and performing a validity check on the at least one command statement based on the configuration file.
    Type: Application
    Filed: January 8, 2021
    Publication date: February 2, 2023
    Inventor: Yun XIE
  • Publication number: 20220321864
    Abstract: The present disclosure relates to the field of visual images. A stereoscopic display screen includes: an optical component, configured to provide an optical signal of which the light intensity is lower than the light intensity of video information; a transparent display component, configured to display the video information; and a space imaging frame component, configured to form a hollow enclosed cavity which is visible from the front and has a rear end sealed by the transparent display component. A foreground stage imaging area is formed in an internal region of the space imaging frame component, the space imaging frame component forms, at a position opposite the optical component, a virtual space imaging frame component which takes an axial plane of the transparent display component as a mirror symmetrical plane, and a virtual background stage imaging area is formed in the virtual space imaging frame component.
    Type: Application
    Filed: June 9, 2022
    Publication date: October 6, 2022
    Inventor: Yun XIE
  • Patent number: 10177246
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a plurality of dummy gates on a substrate, a capping layer on each dummy gate, and a dielectric layer over the substrate, wherein the dielectric layer has a top surface above each dummy gate. The method also includes performing a first ion implantation process on the dielectric layer to form a first stop layer in the dielectric layer. A top surface of the first stop layer is above or coplanar with a top surface of each dummy gate. Further, the method includes performing a first planarization process on the capping layer and the dielectric layer to expose the top surface of each dummy gate. A removal rate of the first stop layer is smaller than a removal rate of the dielectric layer when performing the first planarization process.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: January 8, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Xin Yun Xie
  • Publication number: 20180047623
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a base substrate, including a substrate, a gate structure on the substrate, source and drain doped regions in the substrate on both sides of the gate structure, and a dielectric layer on the substrate and on top of the gate structure. The method also includes forming a contact hole, penetrating through the dielectric layer, wherein a bottom of the contact hole extends into each of the source and drain doped regions. In addition, the method includes forming a doped layer, in each of the source and drain doped regions by a doping process via the bottom and a portion of sidewalls of the contact hole. Further, the method includes forming a conductive plug in the contact hole.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 15, 2018
    Inventor: Xin Yun XIE
  • Publication number: 20180047831
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a plurality of dummy gates on a substrate, a capping layer on each dummy gate, and a dielectric layer over the substrate, wherein the dielectric layer has a top surface above each dummy gate. The method also includes performing a first ion implantation process on the dielectric layer to form a first stop layer in the dielectric layer. A top surface of the first stop layer is above or coplanar with a top surface of each dummy gate. Further, the method includes performing a first planarization process on the capping layer and the dielectric layer to expose the top surface of each dummy gate. A removal rate of the first stop layer is smaller than a removal rate of the dielectric layer when performing the first planarization process.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 15, 2018
    Inventor: Xin Yun XIE
  • Patent number: 9829886
    Abstract: A flight control system is provided. The system includes a primary circuit board, a secondary circuit board electrically connected to the primary circuit board, a system on chip (SOC) integrated chip, a power management chip configured to supply power to the SOC integrated chip, an electronic speed control (ESC) driving circuit module configured to control flight speed in response to an instruction from the SOC integrated chip. In the system, the SOC integrated chip and the power management chip are arranged on the primary circuit board, and the ESC driving circuit module is arranged on the secondary circuit board.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: November 28, 2017
    Assignee: ZEROTECH (SHENZHEN) INTELLIGENCE ROBOT CO., LTD.
    Inventors: Jianjun Yang, Shijun Wu, Hao Wang, Jun Li, Yun Xie
  • Publication number: 20170196087
    Abstract: A flight control system is provided. The system includes a primary circuit board, a secondary circuit board electrically connected to the primary circuit board, a system on chip (SOC) integrated chip, a power management chip configured to supply power to the SOC integrated chip, an electronic speed control (ESC) driving circuit module configured to control flight speed in response to an instruction from the SOC integrated chip. In the system, the SOC integrated chip and the power management chip are arranged on the primary circuit board, and the ESC driving circuit module is arranged on the secondary circuit board.
    Type: Application
    Filed: April 29, 2016
    Publication date: July 6, 2017
    Inventors: Jianjun Yang, Shijun Wu, Hao Wang, Jun Li, Yun Xie
  • Patent number: D803450
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: November 21, 2017
    Assignee: Shenzhen Derl Technology Co., Ltd.
    Inventors: Yun Xie, Deng Pan
  • Patent number: D840699
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 19, 2019
    Assignee: SHENZHEN DERL TECHNOLOGY CO., LTD.
    Inventor: Yun Xie
  • Patent number: D860211
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 17, 2019
    Inventor: Yun Xie
  • Patent number: D922491
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 15, 2021
    Inventor: Yun Xie
  • Patent number: D1006882
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: December 5, 2023
    Inventor: Yun Xie
  • Patent number: D1023424
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: April 16, 2024
    Inventors: Yun Xie, Deng Pan
  • Patent number: D1040916
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: September 3, 2024
    Inventor: Yun Xie
  • Patent number: D1045186
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: October 1, 2024
    Inventors: Yun Xie, Deng Pan