Patents by Inventor Yun Xue
Yun Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968050Abstract: Example methods and apparatus for transmitting ACK/NACK information for data are disclosed. One method includes sending a data packet from a base station to a user equipment. A control signaling is transmitted from the base station to the user equipment and is used to indicate a subframe to be used by the user equipment to send ACK/NACK information corresponding to the data packet.Type: GrantFiled: October 10, 2016Date of Patent: April 23, 2024Assignee: Huawei Technologies Co., Ltd.Inventors: Yifan Xue, Yun Liu, Da Wang, Jian Wang, Yongbo Zeng
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Publication number: 20240097858Abstract: The method includes: sending first resource information on a first sidelink transmission channel, where the first resource information indicates a first resource; and receiving indication information on a second sidelink transmission channel, where the indication information indicates at least one second resource in the first resource; or receiving data sent on a second resource, where the second resource is determined based on the first resource.Type: ApplicationFiled: November 23, 2021Publication date: March 21, 2024Inventors: Yun Liu, Lixia Xue
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Publication number: 20240078566Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to detect promotion events. An apparatus includes interface circuitry to obtain aligned sales data corresponding to products, the products corresponding to a market and a category; computer readable instructions; and programmable circuitry to instantiate event detection circuitry to: identify product-level promotions based on the aligned sales data and corresponding baseline data for the products; and group ones of the product-level promotions to identify promotion events; and expansion circuitry to determine uplift factors for different promotion characteristics based on the market and the category; and apply the uplift factors to the product-level promotions and the promotion events to identify incremental sales.Type: ApplicationFiled: May 31, 2023Publication date: March 7, 2024Inventors: Sam Colalillo, Eric Rossignol, Anne Pietrement, Doreen Stahl, Markus Bleck, Kai Kopperschmidt, Yun Xue
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Patent number: 11658239Abstract: The present disclosure provides a semiconductor device and a fabrication method. The semiconductor device includes: a substrate; a first well region in the substrate, having first ions; an isolation layer in the first well region; a second well region and a third well region, formed in the first well region, located respectively on opposite sides of the isolation layer, having second ions with an opposite conductivity type as the first ions, and with a minimum distance from the isolation layer greater than zero; a first gate structure on the second well region and the first well region; a second gate structure on the third well region and the first well region; a barrier gate on the isolation layer, located between the first gate structure and the second gate structure, and having the second ions; and source-drain doped layers in the second well region and the third well region, respectively.Type: GrantFiled: January 10, 2020Date of Patent: May 23, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Xuemei Wang, Fugang Chen, Yun Xue
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Publication number: 20230054326Abstract: A probiotic composition for treating rapid eye movement sleep behavior disorder, is prepared from Bacillus licheniformis, Bifidobacterium longum, Lactobacillus acidophilus, Enterococcus faecalis, and pharmaceutically acceptable adjuvants. The probiotic composition can improve the symptoms of rapid eye movement sleep behavior disorder of a patient, improve RBD symptoms of idiopathic RBD patients and PD patients, improve the motor symptoms and reduce the daily levodopa equivalent dose in PD patients.Type: ApplicationFiled: October 6, 2022Publication date: February 23, 2023Applicant: BEIJING FRIENDSHIP HOSPITAL AFFILIATED TO CAPITAL MEDICAL UNIVERSITYInventors: Houzhen TUO, Yitong DU, Xiaojiao XU, Yue LI, Mingkai ZHANG, Ying CUI, Yun XUE, Dan GAO, Ting GAO, Zhi SHENG
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Publication number: 20220351221Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to determine headroom. An example apparatus disclosed herein includes a data retriever to retrieve a first data set and a second data set, the first and second data sets including observations, an overlap calculator to merge respective ones of the observations to form an overlap data set, the respective ones of the observations merged based on first tier parameters, a similarity calculator to calculate similarity scores for pairs of the respective ones of the observations in the overlap data set, the similarity score based on second tier parameters, and a data joiner to associate respective ones of the similarity scores with corresponding households associated with the respective ones of the observations.Type: ApplicationFiled: July 8, 2020Publication date: November 3, 2022Inventors: Michael Zenor, John Mansour, Yun Xue
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Publication number: 20200251589Abstract: The present disclosure provides a semiconductor device and a fabrication method. The semiconductor device includes: a substrate; a first well region in the substrate, having first ions; an isolation layer in the first well region; a second well region and a third well region, formed in the first well region, located respectively on opposite sides of the isolation layer, having second ions with an opposite conductivity type as the first ions, and with a minimum distance from the isolation layer greater than zero; a first gate structure on the second well region and the first well region; a second gate structure on the third well region and the first well region; a barrier gate on the isolation layer, located between the first gate structure and the second gate structure, and having the second ions; and source-drain doped layers in the second well region and the third well region, respectively.Type: ApplicationFiled: January 10, 2020Publication date: August 6, 2020Inventors: Xuemei WANG, Fugang CHEN, Yun XUE
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Patent number: 9735094Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.Type: GrantFiled: June 24, 2016Date of Patent: August 15, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yueh-Se Ho, Hamza Yilmaz, Yan Yun Xue, Jun Lu
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Publication number: 20160307830Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Yueh-Se Ho, Hamza Yilmaz, Yan Yun Xue, Jun Lu
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Patent number: 9437528Abstract: A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at top surface is flipped and attached to a die paddle of a lead frame and then is encapsulated with a first molding compound. The first molding compound and the die are ground to reduce the thickness. A mask is applied atop the lead frame with the back of the flipped die exposed and a metal layer is deposited on the exposed area at the back of the flipped die. A metal clip is attached to the back of the flipped die. A second molding compound is deposited on the lead frame with the top surface of the metal clip exposed from the top surface of the second molding compound and the bottom surface of the lead frame exposed from the bottom surface of the second plastic molding compound.Type: GrantFiled: September 22, 2015Date of Patent: September 6, 2016Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Yuping Gong, Xiaoming Sui, Yan Yun Xue, Jun Lu
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Patent number: 9437530Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.Type: GrantFiled: August 11, 2015Date of Patent: September 6, 2016Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yueh-Se Ho, Hamza Yilmaz, Yan Yun Xue, Jun Lu
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Patent number: 9276828Abstract: A method is provided in one example embodiment executed at a service metering framework (SMF) engine including a processor, and includes interfacing, by an event listener at the SMF engine, with an application being executed in a cloud by a remote client device, detecting a metering event associated with the application during execution of the application, receiving a value of at least one metering attribute associated with the metering event, and storing the at least one metering attribute and the value as a formatted metered record in a SMF database searchable according to the metering attribute. In a specific embodiment, the event listener exposes an application programming interface (API) of the SMF engine to the application to facilitate definitions of the metering event and the at least one metering attribute in the application.Type: GrantFiled: February 4, 2015Date of Patent: March 1, 2016Assignee: CISCO TECHNOLOGY, INC.Inventors: Gunupuree Ravi, Meghana S. Joglekar, Sahil Sharma, Yun Xue, Alok Batra
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Publication number: 20150357267Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.Type: ApplicationFiled: August 11, 2015Publication date: December 10, 2015Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Yueh-Se Ho, Hamza Yilmaz, Yan Yun Xue, Jun Lu
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Publication number: 20150149628Abstract: A method is provided in one example embodiment executed at a service metering framework (SMF) engine including a processor, and includes interfacing, by an event listener at the SMF engine, with an application being executed in a cloud by a remote client device, detecting a metering event associated with the application during execution of the application, receiving a value of at least one metering attribute associated with the metering event, and storing the at least one metering attribute and the value as a formatted metered record in a SMF database searchable according to the metering attribute. In a specific embodiment, the event listener exposes an application programming interface (API) of the SMF engine to the application to facilitate definitions of the metering event and the at least one metering attribute in the application.Type: ApplicationFiled: February 4, 2015Publication date: May 28, 2015Applicant: CISCO TECHNOLOGY, INC.Inventors: Gunupuree Ravi, Meghana S. Joglekar, Sahil Sharma, Yun Xue, Alok Batra
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Patent number: 8983987Abstract: A method is provided in one example embodiment and includes causing generation of a metered record associated with a metering event of an application executed within a cloud-based computing system, the metered record including a metering attribute and a corresponding value, the corresponding value being determined substantially simultaneous to a runtime execution of the application, and facilitating searching for the metered record based on the metering attribute and the corresponding value of the metering attribute. In specific embodiments, the metered record is communicated using a REpresentational State Transfer (REST) Application Programming Interface (API). In an example embodiment, the notification of the metering event can be received by any one of a REST API, a Java Messaging Service listener, an Extensible Messaging and Presence Protocol (XMPP) listener, or a metering plugin.Type: GrantFiled: December 5, 2012Date of Patent: March 17, 2015Assignee: Cisco Technology, Inc.Inventors: Gunupuree Ravi, Meghana S. Joglekar, Sahil Sharma, Yun Xue, Alok Batra
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Publication number: 20140032531Abstract: A method is provided in one example embodiment and includes causing generation of a metered record associated with a metering event of an application executed within a cloud-based computing system, the metered record including a metering attribute and a corresponding value, the corresponding value being determined substantially simultaneous to a runtime execution of the application, and facilitating searching for the metered record based on the metering attribute and the corresponding value of the metering attribute. In specific embodiments, the metered record is communicated using a REpresentational State Transfer (REST) Application Programming Interface (API). In an example embodiment, the notification of the metering event can be received by any one of a REST API, a Java Messaging Service listener, an Extensible Messaging and Presence Protocol (XMPP) listener, or a metering plugin.Type: ApplicationFiled: December 5, 2012Publication date: January 30, 2014Applicant: Cisco Technology, Inc.Inventors: Gunupuree Ravi, Meghana S. Joglekar, Sahil Sharma, Yun Xue, Alok Batra
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Publication number: 20120046773Abstract: A mold design system includes an electrode design module, and a central control module. The electrode design module generates a drawing of a mold based on electrode structure parameters. The central control module generates a computerized numerical control (CNC) task, a simulating task, and a testing task according to the drawing generated by the electrode design module.Type: ApplicationFiled: April 29, 2011Publication date: February 23, 2012Applicants: FIH (HONG KONG) LIMITED, SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD.Inventors: ZI-ZHUAN GUI, YUN-XUE HU, XIAO-MING HU, TIAN-CHENG HUANG, PENG YUAN