Patents by Inventor Yun Y. Wang
Yun Y. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10192887Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.Type: GrantFiled: November 20, 2017Date of Patent: January 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
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Publication number: 20180090516Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.Type: ApplicationFiled: November 20, 2017Publication date: March 29, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
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Patent number: 9905694Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.Type: GrantFiled: March 13, 2017Date of Patent: February 27, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Henry K. Utomo, Reinaldo A. Vega, Yun Y. Wang
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Publication number: 20180026137Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.Type: ApplicationFiled: March 13, 2017Publication date: January 25, 2018Inventors: Henry K. Utomo, Reinaldo A. Vega, Yun Y. Wang
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Patent number: 9853055Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.Type: GrantFiled: March 30, 2016Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
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Publication number: 20170287942Abstract: The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.Type: ApplicationFiled: March 30, 2016Publication date: October 5, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Yun Y. Wang, Oh-Jung Kwon, Stephen G. Fugardi, Sean M. Dillon
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Patent number: 9680019Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.Type: GrantFiled: July 20, 2016Date of Patent: June 13, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Henry K. Utomo, Reinaldo A. Vega, Yun Y. Wang
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Publication number: 20140206190Abstract: Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed, causing the semiconductor substrate to react with the metal layer forming a metal-rich silicide layer on the semiconductor substrate. Embodiments may also include forming a low-oxygen capping layer above the metal layer prior to annealing the semiconductor substrate to protect the metal layer from oxidation. The low-oxygen capping layer may, for example, be made of titanium nitride containing less than 20 parts per million of oxygen. Embodiments may further include forming a silicide layer using the above process in a contact hole above a source/drain region of a field-effect transistor, and forming a metal contact above the silicide layer.Type: ApplicationFiled: January 23, 2013Publication date: July 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: BAOZHEN LI, YUN Y. WANG, KEITH KWONG HON WONG, CHIH-CHAO YANG
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Patent number: 8288828Abstract: A via contact is provided to a diffusion region at a top surface of a substrate which includes a single-crystal semiconductor region. The via contact includes a first layer which consists essentially of a silicide of a first metal in contact with the diffusion region at the top surface. A dielectric region overlies the first layer, the dielectric region having an outer surface and an opening extending from the outer surface to the top surface of the substrate. A second layer lines the opening and contacts the top surface of the substrate in the opening, the second layer including a second metal which lines a sidewall of the opening and a silicide of the second metal which is self-aligned to the top surface of the substrate in the opening. A diffusion barrier layer overlies the second layer within the opening. A third layer including a third metal overlies the diffusion barrier layer and fills the opening.Type: GrantFiled: September 9, 2004Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Michael M. Iwatake, Kevin E. Mello, Matthew W. Oonk, Amanda L. Piper, Yun Y. Wang, Keith K. Wong
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Patent number: 7750418Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures.Type: GrantFiled: May 22, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri, Yun Y. Wang, Keith Kwong Hon Wong
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Patent number: 7425497Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures.Type: GrantFiled: January 20, 2006Date of Patent: September 16, 2008Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri, Yun Y. Wang, Keith Kwong Hon Wong
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Publication number: 20080217747Abstract: Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures.Type: ApplicationFiled: May 22, 2008Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri, Yun Y. Wang, Keith Kwong Hon Wong