Patents by Inventor Yun-Yan Chung

Yun-Yan Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20230253503
    Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 10, 2023
    Inventors: Yun-Yan Chung, Chao-Ching Cheng, Chao-Hsin Chien
  • Semiconductor device and method
    Patent number: 11670720
    Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yan Chung, Chao-Ching Cheng, Chao-Hsin Chien
  • MEMORY DEVICE, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF MEMORY DEVICE
    Publication number: 20220344357
    Abstract: A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Yan Chung, Chao-Ching Cheng
  • Semiconductor Device and Method
    Publication number: 20220165871
    Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.
    Type: Application
    Filed: May 19, 2021
    Publication date: May 26, 2022
    Inventors: Yun-Yan Chung, Chao-Ching Cheng, Chao-Hsin Chien