Abstract: A method for manufacturing a semiconductor device, including forming a step key on a substrate, forming a mold layer on the step key covering the step key, forming a first mask layer on the mold layer, forming a transparent layer in the first mask layer overlapping the step key, forming a second mask layer on the first mask layer and the transparent layer, etching the mold layer using the second mask layer, wherein the first mask layer includes a metal material.

Abstract: Provided is a novel compound capable of improving the luminous efficiency, stability and life span of a device, an organic electric element using the same, and an electronic device thereof.

Abstract: The present invention relates to a composition, a kit, a nucleic acid chip and a method, for diagnosing colorectal cancer, rectal cancer or colorectal adenoma by detecting the methylation level of CpG sites in a LINC01798 gene, in which colorectal cancer, rectal cancer, or colorectal adenoma can not only be diagnosed accurately and rapidly, but can also be diagnosed early.

Abstract: The present invention relates to a composition, a kit, a nucleic acid chip, and a method capable of diagnosing colorectal cancer, rectal cancer, or colorectal adenoma by detecting the methylation level of CpG sites in a GLRB gene. Accordingly, colorectal cancer, rectal cancer, or colorectal adenoma can be diagnosed not only accurately and quickly, but also at an early stage.

Abstract: A memory device includes an error correction code (ECC) block suitable for performing an ECC operation, and generating a flag signal when an error is detected and corrected through the ECC operation in data read from a memory cell array, and a refresh control block suitable for comparing an active row address with a target address in response to the flag signal, and refreshing data of a neighboring address of the target address based on a comparison result.

Abstract: A memory device includes an error correction code (ECC) block suitable for performing an ECC operation, and generating a flag signal when an error is detected and corrected through the ECC operation in data read from a memory cell array, and a refresh control block suitable for comparing an active row address with a target address in response to the flag signal, and refreshing data of a neighboring address of the target address based on a comparison result.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: The present invention provides a novel class of macrocyclic compounds, which are useful as cysteine protease inhibitors. Also provided are novel intermediates and methods of preparing the compounds. The invention also provides pharmaceutical compositions comprising the compounds. The compounds and compositions are useful in methods of treating or preventing one or more diseases associated with cysteine protease activity, particularly those associated with calpain activity.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: Provided is a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first cell array, a first fuse circuit, a first spare cell array, a second spare cell array, and a redundancy select controller. The first fuse circuit may be configured to store a first failed address corresponding to one or more defective memory cells in the first cell array. Each of the first and second spare cell arrays may include a plurality of spare memory cells configured to replace first and second defective memory cells in the first cell array, respectively. For replacing the first and second defective memory cells, the redundancy select controller may be configured to selectively assign the first fuse circuit to either one or both of the first and second spare cell arrays.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Abstract: The present invention provides a novel class of macrocyclic compounds, which are useful as cysteine protease inhibitors. Also provided are novel intermediates and methods of preparing the compounds. The invention also provides pharmaceutical compositions comprising the compounds. The compounds and compositions are useful in methods of treating or preventing one or more diseases associated with cysteine protease activity, particularly those associated with calpain activity.

Abstract: The present invention provides a novel class of macrocyclic compounds, which are useful as cysteine protease inhibitors. Also provided are novel intermediates and methods of preparing the compounds. The invention also provides pharmaceutical compositions comprising the compounds. The compounds and compositions are useful in methods of treating or preventing one or more diseases associated with cysteine protease activity, particularly those associated with calpain activity.

Abstract: Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.