Patents by Inventor Yun Yu

Yun Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137412
    Abstract: Provided is a collaborative application service process management system based on a multi-tenant mode in an embodiment of the present disclosure. The system includes an application module, an application service process phase module, an application service process phase state module, an application object module, a collaborative application object management module, an application permission module, an application service process re-combiner, a shared database, etc. According to the method, a service process satisfying multi-scenario requirements can be designed in combination with an actual application scenario, and multi-scenario services in one application can be collaboratively managed. Therefore, system switch between different scenarios by a tenant is reduced, an inter-tenant collaborative management capacity is improved, and a tenant-application multi-scenario management capacity is improved.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 25, 2024
    Inventor: Yun YU
  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240128231
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Fu Wei Liu, Pei-Wei Lee, Yun-Chung Wu, Bo-Yu Chiu, Szu-Hsien Lee, Mirng-Ji Lii
  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Patent number: 11963450
    Abstract: A method for manufacturing a core-shell coaxial gallium nitride (GaN) piezoelectric nanogenerator is provided. A mask covering a center part of a gallium nitride wafer is removed. An electrodeless photoelectrochemical etching is performed on the gallium nitride wafer to form a primary GaN nanowire array on a surface of the gallium nitride wafer. A precious metal layer provided on the surface of the gallium nitride wafer is removed and an alumina layer is deposited on the surface of the gallium nitride wafer to cover the primary GaN nanowire array to obtain a core-shell coaxial GaN nanowire array. A first conductive layer is provided on a flexible substrate to which the core-shell coaxial GaN nanowire array is transferred. A second conductive layer is provided at a top end of the core-shell coaxial GaN nanowire array, and is connected to an external circuit to obtain the core-shell coaxial GaN piezoelectric nanogenerator.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: April 16, 2024
    Assignee: Guangdong University of Technology
    Inventors: Yun Chen, Pengfei Yu, Aoke Song, Zijian Li, Maoxiang Hou, Xin Chen
  • Patent number: 11963300
    Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 16, 2024
    Assignee: Au Optronics Corporation
    Inventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
  • Publication number: 20240117362
    Abstract: Embodiments of the present disclosure relate to lipid-PEGylated solid support and phosphoramidites derivatives, methods for preparing the same, and their uses in the delivery of oligonucleotide drugs to the cellular targets.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 11, 2024
    Inventors: Mufa Zou, David Yu, Aldrich N.K. Lau, Ruiming Zou, Wing C. Poon, Gang Zhao, Gengyu Du, Yun-Chiao Yao, Allen Wong, Xiaojun Li
  • Publication number: 20240119836
    Abstract: Disclosed is a method for providing real-time bus information by a terminal, the method including: receiving ultra-precise bus information about buses scheduled to arrive at a bus stop from a server; and based on the ultra-precise bus information, displaying at least one bus which moves toward the bus stop and disappears after passing the bus stop on a map area.
    Type: Application
    Filed: June 22, 2023
    Publication date: April 11, 2024
    Inventors: Sukyung SON, Rakmin SUNG, Daehyun IM, Gyeonghyeon MOON, Yun Hee JUNG, Jaesung CHOI, Seoha YU, Binnara LEE, Jaiwuk CHUNG, Sung Hyeok PARK, Jinwoo KIM, Shin Hyun KIM, Gahee JEONG
  • Patent number: 11954758
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for dynamic wave pairing. A graphics processor may allocate one or more GPU workloads to one or more wave slots of a plurality of wave slots. The graphics processor may select a first execution slot of a plurality of execution slots for executing the one or more GPU workloads. The selection may be based on one of a plurality of granularities. The graphics processor may execute, at the selected first execution slot, the one or more GPU workloads at the one of the plurality of granularities.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 9, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Andrew Evan Gruber, Zilin Ying, Chunling Hu, Baoguang Yang, Yang Xia, Gang Zhong, Chun Yu, Eric Demers
  • Patent number: 11949827
    Abstract: Various embodiments disclose a method for operating a printer apparatus that includes a print head. The method includes causing a media hub to retract a media in a retract direction along a media path. Further, the method includes causing a first media sensor to generate a first signal during retraction of the media. Furthermore, the method includes monitoring the first signal to detect at least one of a leading edge or a trailing edge of a label of the plurality of labels. Upon detecting the at least one of the leading edge or the trailing edge of the label, causing the media hub to retract the media by at least a predetermined distance, wherein the predetermined distance is a distance between the print head and the first media sensor.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: April 2, 2024
    Assignee: Hand Held Products, Inc.
    Inventors: Ramanathan Alaganchetty, Boon Kheng Lim, Rajan Narayanaswami, Qibao Yu, Jian Zeng, Hongqiang Liu, Quanjin Shi, Zhiyong Zhu, Yun Huang, Xiaoming Yuan
  • Publication number: 20240103220
    Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 28, 2024
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
  • Publication number: 20240094791
    Abstract: In one embodiment, a printed circuit board (PCB) includes a substrate, one or more signal layers including a first signal layer, a first segment of a transmission line disposed at the first signal layer electrically coupling a first location to a second location, and a first signal via disposed at the second location. The PCB circuit includes a second segment of the transmission line disposed at the first signal layer electrically coupling a third location to a fourth location and a second signal via disposed at the third location. The PCB includes a power-over-cable circuit disposed on a first surface of the substrate and electrically coupled to the first and second signal via, where the first and second segments carry a signal of an image sensor and the first segment carries power from the power-over-cable circuit to the image sensor, where the image sensor is used for an autonomous vehicle.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Inventors: ZHENWEI YU, YUN JI
  • Publication number: 20240096084
    Abstract: Systems and methods for identifying and segmenting objects from images include a preprocessing module configured to adjust a size of a source image; a region-proposal module configured to propose one or more regions of interest in the size-adjusted source image; and a prediction module configured to predict a classification, bounding box coordinates, and mask. Such systems and methods may utilize end-to-end training of the modules using adversarial loss, facilitating the use of a small training set, and can be configured to process historical documents, such as large images comprising text. The preprocessing module within the systems and methods can utilize a conventional image scaler in tandem with a custom image scaler to provide a resized image suitable for GPU processing, and the region-proposal module can utilize a region-proposal network from a single-stage detection model in tandem with a two-stage detection model paradigm to capture substantially all particles in an image.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: Ancestry.com Operations Inc.
    Inventors: Masaki Stanley Fujimoto, Yen-Yun Yu
  • Publication number: 20240096941
    Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 21, 2024
    Inventors: SHIH-JUNG TU, PO-WEI LIU, TSUNG-YU YANG, YUN-CHI WU, CHIEN HUNG LIU
  • Publication number: 20240092817
    Abstract: Embodiments of the present application relate to polymers used as polymeric polyvalent hub for liquid phase oligonucleotide synthesis. Methods for making an oligonucleotide by liquid phase oligonucleotide synthesis using the polyvalent hub are also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 21, 2024
    Inventors: Gaomai Yang, Yun-Chiao Yao, David Yu, Aldrich N.K. Lau
  • Patent number: 11936927
    Abstract: A multimedia signal transmission control system is provided, which includes a transmitter control circuit and a receiver control circuit coupled with each other. The transmitter control circuit packs a control signal and at least one of multimedia signals into first hybrid data packets in an active video period of a video frame, and packs the control signal and another at least one of the multimedia signals into second hybrid data packets in a vertical front porch and a vertical back porch of the video frame. The receiver control circuit receives the first hybrid data packets in the active video period, and receives the second hybrid data packets in the vertical front porch and the vertical back porch. The receiver control circuit unpacks the first hybrid data packets and the second hybrid data packets to provide the control signal and the multimedia signals to a display module.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 19, 2024
    Assignee: Realtek Semiconductor Corporation
    Inventors: Yun-Hung Lin, Po-Hsien Wu, Li-Yu Chen
  • Patent number: 11936861
    Abstract: Embodiments of this application relate to the video coding and compression field, and disclose an encoding method and apparatus, and a decoding method and apparatus, to resolve a problem that an existing split mode cannot satisfy a relatively complex texture requirement. The decoding method specifically includes: parsing a bitstream to determine a basic split mode for a current to-be-decoded picture block and a target derivation mode for a subpicture block of the current to-be-decoded picture block; splitting the current to-be-decoded picture block into N subpicture blocks in the basic split mode, where N is an integer greater than or equal to 2; deriving one derived picture block from at least two adjacent subpicture blocks in the N subpicture blocks in the target derivation mode; and decoding the derived picture block.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: March 19, 2024
    Assignees: Huawei Technologies Co., Ltd., Tsinghua University
    Inventors: Quanhe Yu, Jicheng An, Jianhua Zheng, Yongbing Lin, Liqiang Wang, Benben Niu, Ziwei Wei, Yun He
  • Publication number: 20240086692
    Abstract: A semiconductor device may include a non-volatile memory cell structure that may be formed in a back end region of a semiconductor device. The non-volatile memory cell structure may include a floating gate structure in which a portion of a dielectric layer is included between a gate structure and a word line conductive structure. The separation of the gate structure and the word line conductive structure by the dielectric layer results in the gate structure being a floating gate structure. This enables a charge to be selectively stored on the gate structure, even when power is removed from the word line conductive structure. The non-volatile memory cell structure along with a volatile memory cell structure are provided in the back end region of the semiconductor device, such that caching and long-term storage may be performed in the back end region of the semiconductor device.
    Type: Application
    Filed: January 5, 2023
    Publication date: March 14, 2024
    Inventors: Yun-Feng KAO, Katherine H. CHIANG, Chia Yu LING
  • Publication number: 20240085447
    Abstract: An inertial measurement unit (IMU) device includes an IMU sensor, a controller, a temperature sensor electrically connected to the controller, a heat source, and a heat conductive member. The controller is configured to, in response to a temperature of the IMU sensor detected by the temperature sensor falling below a threshold temperature, control the heat source to generate heat. The heat conductive member is configured to transfer heat from the heat source to the IMU sensor, and includes an electrically insulating and thermally conductive material.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Guoxiu PAN, Yonggen WANG, Yun YU, Peng ZHANG
  • Publication number: 20240087989
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Josh LIN, Chung-Jen HUANG, Yun-Chi WU, Tsung-Yu YANG