Patents by Inventor Yun-Yu Hsieh

Yun-Yu Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021474
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Lid.
    Inventors: Yun-Yu HSIEH, Ying Ting HSIA, Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU
  • Patent number: 11776847
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20210366770
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 11139174
    Abstract: A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xi-Zong Chen, Yun-Yu Hsieh, Cha-Hsin Chao, Li-Te Hsu
  • Patent number: 11088025
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20200286781
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu HSIEH, Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU, Ying Ting HSIA
  • Patent number: 10679896
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Publication number: 20200118825
    Abstract: A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Xi-Zong Chen, Yun-Yu Hsieh, Cha-Hsin Chao, Li-Te Hsu
  • Patent number: 10515817
    Abstract: A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xi-Zong Chen, Yun-Yu Hsieh, Cha-Hsin Chao, Li-Te Hsu
  • Publication number: 20190103281
    Abstract: A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.
    Type: Application
    Filed: July 6, 2018
    Publication date: April 4, 2019
    Inventors: Xi-Zong Chen, Yun-Yu Hsieh, Cha-Hsin Chao, Li-Te Hsu
  • Publication number: 20190088542
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 21, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
  • Patent number: 10083863
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia