Patents by Inventor Yun-Yu Wang

Yun-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071758
    Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.
    Type: Application
    Filed: September 23, 2022
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, You-Jia Chang, Bo-Yu Chen, Yun-Chun Wang, Ruey-Chyr Lee, Wen-Jung Liao
  • Patent number: 10566446
    Abstract: Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun-Yu Wang, Jochonia Nxumalo, Ahmad Katnani, Dimitrios Ioannou, Kenneth Bandy, Jeffrey Brown, Michael J. MacDonald
  • Publication number: 20190371918
    Abstract: Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 5, 2019
    Inventors: Yun-Yu Wang, Jochonia Nxumalo, Ahmad Katnani, Dimitrios Ioannou, Kenneth Bandy, Jeffrey Brown, Michael J. MacDonald
  • Patent number: 9953927
    Abstract: Structures for a liner replacement in an interconnect structure and methods for forming a liner replacement in an interconnect structure. A metallization level is formed that includes a conductive feature. A dielectric layer is formed on the metallization level. The dielectric layer includes an opening that extends vertically through the dielectric layer to the conductive feature. An adhesion layer is formed on area of the conductive feature exposed at a base of the opening. The adhesion layer has a thickness equal to a monolayer or a fraction of a monolayer. Another layer (e.g., barrier layer) of a different composition (e.g., TiN) may be deposited on the adhesion layer before the opening is filled with metal deposited by chemical vapor deposition.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yun-Yu Wang, Daniel P. Stambaugh, Jeffrey Brown, Keith Kwong Hon Wong
  • Patent number: 9685553
    Abstract: Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel region underneath a gate structure, and a source region and a drain region directly adjacent to the fin channel region at two opposing sides of the gate structure; and subjecting the source region and the drain region to a compressive strain; thereby causing the source region and the drain region to exert a tensile strain to the fin channel region. A finFET transistor formed thereby is also provided, which includes a channel region of fin shape covered by a gate on top thereof; a source next to a first end of the channel region on a first side of the gate; and a drain next to a second end of the channel region on a second side of the gate, wherein the source and drain are made of epitaxially grown silicon-germanium (SiGe) having a Ge concentration level of at least 50% atomic percentage covered with silicon cap.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: June 20, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yun-Yu Wang, Shogo Mochizuki
  • Publication number: 20170154687
    Abstract: A SRAM-like electron beam inspection (EBI) structure and method for determining defects in integrated circuits inline during the production process at a level that enables earlier detection during fabrication. Initial layers, such as active layer, poly gate and contact of an IC are first fabricated, and a conductive mesh with horizontal components is provided above the contact layers connecting contact nodes of the contact layers. Voltage contrast is observed during EBI to detect short-circuits, open-circuits, or leakage currents formed between the horizontal components of the conductive mesh and metallized islands placed therebetween.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Zhigang Song, Oliver D. Patterson, Yun-Yu Wang, Keith Kwong Hon Wong
  • Patent number: 9551674
    Abstract: An inline dark field holographic method for measuring strain in a semiconductor or other crystalline material using a transmission electron microscope having an electron gun for passing an electron beam through strained and unstrained specimens. A condenser mini-lens between the magnetic tilting coil and the specimens increases defection of the beam at an angle with prior to passing through the pair of specimens. The first objective lens forms a virtual image of each of the specimens and the second objective lens focuses the virtual images of each of the specimens at an intermediate image plane to form intermediate images of each of the specimens. The biprism creates the interference pattern between the specimens is formed at the image plane, which may then be viewed to determine the degree of strain of the strained specimen and provides a coma-free strain map with minimal optical distortion.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: January 24, 2017
    Assignee: GlobalFoundries, Inc.
    Inventors: Yun-Yu Wang, John Bruley
  • Publication number: 20160372598
    Abstract: Embodiments of the present invention provide a method of forming fin-type transistors. The method includes forming a finFET structure having a fin channel region underneath a gate structure, and a source region and a drain region directly adjacent to the fin channel region at two opposing sides of the gate structure; and subjecting the source region and the drain region to a compressive strain; thereby causing the source region and the drain region to exert a tensile strain to the fin channel region. A finFET transistor formed thereby is also provided, which includes a channel region of fin shape covered by a gate on top thereof; a source next to a first end of the channel region on a first side of the gate; and a drain next to a second end of the channel region on a second side of the gate, wherein the source and drain are made of epitaxially grown silicon-germanium (SiGe) having a Ge concentration level of at least 50% atomic percentage covered with silicon cap.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Yun-Yu Wang, Shogo Mochizuki
  • Patent number: 9275907
    Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kevin K. Chan, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Min Yang, Qi Zhang
  • Patent number: 9105741
    Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Jinghong Li, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Qingyun Yang
  • Patent number: 9023697
    Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Min Yang, Qi Zhang
  • Publication number: 20150076695
    Abstract: A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicants: STMICROELECTRONICS, INC., International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Lawrence A. Clevenger, Terence L. Kane, Carl J. Radens, Andrew H. Simon, Yun-Yu Wang, Yiheng Xu, John Zhang
  • Publication number: 20150041911
    Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Applicants: GLOBALFOUNDRIES, INC., International Business Machines Corporation
    Inventors: KEVIN K. CHAN, DAE-GYU PARK, XINHUI WANG, YUN-YU WANG, MIN YANG, QI ZHANG
  • Publication number: 20150041858
    Abstract: A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region.
    Type: Application
    Filed: October 24, 2014
    Publication date: February 12, 2015
    Inventors: KEVIN K. CHAN, DAE-GYU PARK, XINHUI WANG, YUN-YU WANG, MIN YANG, QI ZHANG
  • Patent number: 8901674
    Abstract: A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Keith Kwong Hon Wong, Dechao Guo, Unoh Kwon, Christopher Carr Parks, Yun-Yu Wang
  • Patent number: 8735243
    Abstract: A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew W. Copel, Bruce B. Doris, Vijay Narayanan, Yun-Yu Wang
  • Publication number: 20140138832
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Patent number: 8729702
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 20, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Publication number: 20140070316
    Abstract: A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Jinghong Li, Dae-Gyu Park, Xinhui Wang, Yun-Yu Wang, Qingyun Yang
  • Patent number: 8536555
    Abstract: A method to form a voltage sensitive resistor (VSR) read only memory (ROM) device on a semiconductor substrate having a semiconductor device including depositing by chemical vapor deposition (CVD) a titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by at least an order of 102 when a predetermined voltage and current are applied to the VSR; and applying a predetermined voltage and current so as to make the CVD titanium nitride less resistive by at least an order of 102.
    Type: Grant
    Filed: March 9, 2013
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Terence L. Kane, Yun-Yu Wang, Keith Kwong Hon Wong