Abstract: The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

Abstract: The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

Abstract: A semiconductor circuit and an operating method for the same are provided. The semiconductor circuit includes strings. The strings include a first string and a second string. The first string includes a first device unit and a second device unit in series. The first string has a weight signal W1. The first device unit has an input signal A. The second device unit has an input signal B. The second string includes a third device unit and a fourth device unit in series. The second string has a weight signal W2. The third device unit has an input signal ?. The fourth device unit has an input signal B. An output signal of the semiconductor circuit is a sum of output string signals of the strings.

Abstract: A biological sample pretreatment device includes a base body and a moveable part. The base body is formed with an elongated accommodation space configured to accommodate a sampling tube and a reaction tube aligned with each other. The moveable part moveably connects to the base body for ejecting the reaction tube from the base body.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

Abstract: The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

Abstract: A monitor supporting device includes an arm module, a connection module, and a pivoting module. The connection module includes a main plate body adapted to be secured to an arm-securing portion of a monitor, and a cable-fixing unit connected to the main plate body. The cable-fixing unit includes an extension arm body that defines a constraining space adapted for passage of a plurality of cables therethrough, and that is adapted for allowing a cable tie to tie and secure the cables thereonto. The pivoting module is connected to the arm module and the main plate body, such that the connection module is pivotable relative to the arm module. A junction of the pivoting module and the main plate body is disposed above the extension arm body.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

Abstract: A memory device is provided. The memory device includes a memory array of a plurality of memory elements, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements includes two memory cells. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

Abstract: A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

Abstract: The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

Abstract: A memory device is provided. The memory device includes a memory array of a plurality of memory elements, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements includes two memory cells. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

Abstract: A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.

Abstract: A method for standardizing image annotation includes receiving a defect pattern; marking an image according to the defect pattern to generate a first judgement result; marking the image according to the defect pattern to generate a second judgement result; comparing the first judgement result and the second judgement result to obtain a comparison result; and updating the defect pattern according to the comparison result to standardize the defect pattern. The method for standardizing image annotation of the present specification can improve the marking stability of the training data of a trained image recognition algorithm, thereby improving the accuracy of image recognition of the trained image recognition algorithm.

Abstract: A method of measuring hematocrit is provided. The method for measuring hematocrit includes the following steps. A test strip is provided. The test strip includes a reaction region and a pair of electrodes disposed in the reaction region. A whole blood sample is entered to the reaction region. After the whole blood sample enters the reaction region, a plurality of sets of square wave voltages are intermittently applied to the pair of electrodes based on a square wave voltammetry method to obtain a plurality of feedbacks related to hematocrit. An interval between two adjacent sets of square wave voltages ranges from 0.1 seconds to 4 seconds. A feedback of an n-th set of square wave voltages is obtained to calculate a hematocrit value of the whole blood sample and n is a positive integer greater than 1. A hematocrit value is calculated according to the feedback.

Abstract: A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.