Patents by Inventor Yun-Zong Tian
Yun-Zong Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8756028Abstract: A fault detection method of semiconductor manufacturing processes is disclosed. The method includes the steps of providing a storage device, collecting a fault detection and classification(FDC) parameter by the storage device, setting up a measurement site for measuring an online measurement parameter, collecting a wafer acceptance test(WAT) in correspondence to the FDC parameter, establishing a first relationship equation between the FDC parameter and the online measurement parameter, establishing a second relationship equation of the online measurement parameter and the WAT by using the first relationship equation, establishing a third relationship equation between the FDC parameter and the WAT, establishing a waning region of the manufacturing processes by using the first, second, and third relationship equations, and determining the situation of generating wafer defects according to the warning region. The present invention discloses a system architecture for the method.Type: GrantFiled: September 22, 2011Date of Patent: June 17, 2014Assignee: Inotera Memories, Inc.Inventors: Yij Chieh Chu, Yun-Zong Tian
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Patent number: 8649990Abstract: A method of detecting variance by regression model has the following steps. Step 1 is preparing the FDC data and WAT data for analysis. Step 2 is figuring out what latent variable effect of WAT data by Factor Analysis Step 3 is utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components. Step 4 is demonstrating how the tools and FDC data affect WAT data by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.Type: GrantFiled: June 28, 2011Date of Patent: February 11, 2014Assignee: Inotera Memories, Inc.Inventors: Yij Chieh Chu, Chun Chi Chen, Yun-Zong Tian
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Patent number: 8510610Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.Type: GrantFiled: September 22, 2011Date of Patent: August 13, 2013Assignee: Inotera Memories, Inc.Inventors: Yij Chieh Chu, Yun-Zong Tian
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Publication number: 20120331357Abstract: The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points representing operational parameter of a semiconductor equipment within a predetermined time period; obtaining an approximation of the raw data points with a Fourier series; computing the Fourier coefficients and the residuals between the raw data points and the corresponding predicted values predicted by the Fourier series; determining if the residuals exceed an error threshold; recording and storing the Fourier coefficients as the compressed data if none of the residuals exceeds the error threshold; and recording the raw data point as abnormal data point if the corresponding residual exceeds the error threshold before recording and storing the Fourier coefficients and the abnormal data point as the compressed data.Type: ApplicationFiled: September 22, 2011Publication date: December 27, 2012Applicant: INOTERA MEMORIES, INC.Inventors: YIJ CHIEH CHU, YUN-ZONG TIAN
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Publication number: 20120330591Abstract: A fault detection method of semiconductor manufacturing processes is disclosed. The method includes the steps of providing a storage device, collecting a fault detection and classification(FDC) parameter by the storage device, setting up a measurement site for measuring an online measurement parameter, collecting a wafer acceptance test(WAT) in correspondence to the FDC parameter, establishing a first relationship equation between the FDC parameter and the online measurement parameter, establishing a second relationship equation of the online measurement parameter and the WAT by using the first relationship equation, establishing a third relationship equation between the FDC parameter and the WAT, establishing a waning region of the manufacturing processes by using the first, second, and third relationship equations, and determining the situation of generating wafer defects according to the warning region. The present invention discloses a system architecture for the method.Type: ApplicationFiled: September 22, 2011Publication date: December 27, 2012Applicant: INOTERA MEMORIES, INC.Inventors: YIJ CHIEH CHU, YUN-ZONG TIAN
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Patent number: 8332416Abstract: A specification establishing method for controlling semiconductor process, the steps includes: sampling a plurality of sample groups from a population, each sample group being a non-normal distribution; filtering the sample groups; summarizing the filtered sample groups to form a non-normal distribution diagram; getting a value-at-risk and a median by calculating from the non-normal distribution diagram; getting a critical value by calculating the value-at-risk and the median with a critical formula; getting a plurality of state values by calculating the filtered sample groups with a proportion formula; and getting an index value by calculating the non-normal distribution diagram with the proportion formula. Thus, the state values indicate the states of the sample groups are abnormal or not by comparing the state values to the index value.Type: GrantFiled: January 11, 2011Date of Patent: December 11, 2012Assignee: Inotera Memories, Inc.Inventors: Cheng-Hao Chen, Yun-Zong Tian, Shih-Chang Kao, Yij Chieh Chu, Wei Jun Chen
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Patent number: 8265903Abstract: A method for assessing data worth for analyzing yield rate includes: getting measured data with data points that corresponds to control variables of semiconductor manufacturing; transforming the data points into a distance matrix with matrix distances corresponding to differences of the data points under the control variables; expressing sample differences recorded in the distance matrix by two-dimension vectors and calculating similarity degrees of the two-dimension vectors and the distance matrix so as to take loss information as a conversion error value; calculating discriminant ability of the transformed two-dimension data and expressing the discriminant ability by an error rate of discriminant; and taking the conversion error value and the error rate of discriminant as penalty terms and calculating a quality score corresponding to the measured data.Type: GrantFiled: July 8, 2009Date of Patent: September 11, 2012Assignee: Inotera Memories, Inc.Inventors: Yij Chieh Chu, Chun Chi Chen, Yun-Zong Tian, Shih Chang Kao, Cheng-Hao Chen
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Patent number: 8244500Abstract: A method of adjusting wafer process sequence includes steps of collecting production parameters for a plurality of lots; selecting a plurality of key parameters from the production parameters, wherein the key parameters at least includes a processing sequence; defining a formula to obtain an epsilon value; categorizing the lots into groups according to the epsilon value and the minimum point number by using density-based spatial clustering of application with noise (DBSCAN); and adjusting the processing sequences of the lots in the groups. Thereby, the lots with the same process recipe can be continuously or simultaneously sent into a machine, thereby reducing replacement of process recipes or shortening machine idle time.Type: GrantFiled: June 2, 2009Date of Patent: August 14, 2012Assignee: Inotera Memories, Inc.Inventors: Yun-Zong Tian, Chun Chi Chen, Yi Feng Lee, Wei Jun Chen, Shih Chang Kao, Yij Chieh Chu, Cheng-Hao Chen
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Patent number: 8195431Abstract: A method for evaluating efficacy of prevention maintenance for a tool includes the steps of: choosing a tool which has been maintained preventively and choosing a productive parameter of the tool; collecting values of the productive parameter generated from the tool during a time range for building a varying curve of the productive parameter versus time, modifying the varying curve with a moving average method; transforming the varying curve into a Cumulative Sum chart; and judging whether the values of the productive parameter generated from the tool after the prevention maintenance are more stable, compared with the values of the productive parameter generated from the tool before the prevention maintenance, according to the Cumulative Sum chart. Thereby, if the varying of the values of the productive parameter after the prevention maintenance isn't stable, then the efficacy of this prevention maintenance for the tool is judged not good.Type: GrantFiled: September 25, 2009Date of Patent: June 5, 2012Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Chun Chi Chen, Shih Chang Kao, Yun-Zong Tian, Wei Jun Chen
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Patent number: 8170964Abstract: A method for planning a semiconductor manufacturing process based on users' demands includes the steps of: establishing a genetic algorithm model and inputting data; establishing a fuzzy system and setting one output parameter representing percent difference of each cost function in neighbor generations; setting to have a modulation parameter corresponding to each input parameter for adjusting fuzzy sets of the output parameter; executing genetic algorithm actions; executing fuzzy inference actions; eliminating chromosomes that produce output parameter smaller than a defined lower limit, and the remaining chromosomes that produces the largest output parameter is defined as the optimum chromosome, wherein the genetic algorithm actions stops being executed upon the optimum chromosome; then determining whether or not a defined number of generations has been reached, if yes, executing the optimum chromosome of the last generation; if no, continuing executing the genetic algorithm actions, thereby finding the optiType: GrantFiled: May 26, 2009Date of Patent: May 1, 2012Assignee: Inotera Memories, Inc.Inventors: Wei Jun Chen, Chun Chi Chen, Yun-Zong Tian, Yi Feng Lee, Tsung-Wei Lin
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Publication number: 20120102052Abstract: A specification establishing method for controlling semiconductor process, the steps includes: providing a database and choosing a population from the database; sampling a plurality of sample groups from the population, each sample group being a non-normal distribution and having a plurality of samples; filtering the sample groups; summarizing the filtered sample groups to form a non-normal distribution diagram; getting a value-at-risk and a median by calculating from the non-normal distribution diagram; getting a critical value by calculating the value-at-risk and the median with a critical formula; getting a plurality of state values by calculating the filtered sample groups with a proportion formula; and getting an index value by calculating the non-normal distribution diagram with the proportion formula. Thus, the state values indicate the states of the sample groups are abnormal or not by comparing the state values to the index value.Type: ApplicationFiled: January 11, 2011Publication date: April 26, 2012Applicant: INOTERA MEMORIES, INC.Inventors: CHENG-HAO CHEN, YUN-ZONG TIAN, SHIH-CHANG KAO, YIJ CHIEH CHU, WEI JUN CHEN
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Patent number: 8090668Abstract: A method for predicting cycle time comprises the steps of: collecting a plurality of known sets of data; using a clustering method to classify the known sets of data into a plurality of clusters; using a decision tree method to build a classification rule of the clusters; building a prediction model of each cluster; preparing data predicted set of data; using the classification rule to determine that to which clusters the predicted set of data belongs; and using the prediction model of the cluster to estimate the objective cycle time of the predicted set of data. Therefore, engineers can beforehand know the cycle time that one lot of wafers spend in the forward fabrication process, which helps engineers to properly arrange the following fabrication process of the lot of wafer.Type: GrantFiled: October 1, 2008Date of Patent: January 3, 2012Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Chun Chi Chen, Yun-Zong Tian, Tsung-Wei Lin
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Publication number: 20110257932Abstract: A method of detecting variance by regression model has the following steps. Step 1 is preparing the FDC data and WAT data for analysis. Step 2 is figuring out what latent variable effect of WAT data by Factor Analysis Step 3 is utilizing Principal Component Analysis to reduce the number of FDC variables to a few independent principal components. Step 4 is demonstrating how the tools and FDC data affect WAT data by Analysis of covariance model, and constructing interrelationship among FDC, WAT and tools. The interrelationship can point out which parameter effect WAT significantly. By the method, when WAT abnormal situation happened, it is easier for engineers to trace where the problem is.Type: ApplicationFiled: June 28, 2011Publication date: October 20, 2011Applicant: INOTERA MEMORIES, INC.Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN
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Publication number: 20110251708Abstract: A method for planning a production schedule of equipment includes: receiving information about a material replacement of the equipment; and determining a target production schedule of the equipment according to the information about the material replacement of the equipment, wherein the target production schedule includes an idle period, and during the idle period, the equipment stops manufacturing under a normal state.Type: ApplicationFiled: May 19, 2010Publication date: October 13, 2011Inventors: Wei-Jun Chen, Yun-Zong Tian, Yij-Chieh Chu, Yi-Feng Lee
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Patent number: 8032248Abstract: A method for finding the correlation between tool PM (prevention maintenance) and the product yield of the tool is disclosed. The method uses a moving average method to magnify a curve trend that is formed by the product yield data that is captured during a predetermined days before PM and after PM. The magnified curve trend is shown by a Cumulative sum chart. The Cumulative sum chart is analyzed for informing related workers of the effect between the tool PM and the product yield, so as to accurately estimate PM timing. Thereby, via the method, the effect between the tool PM and the product yield may be determined, which serves as an important reference for workers to execute further PM.Type: GrantFiled: July 22, 2009Date of Patent: October 4, 2011Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Chun Chi Chen, Yun-Zong Tian, Wei Jun Chen, Tsung-Wei Lin
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Patent number: 8010212Abstract: A method of fuzzy control for adjusting a semiconductor machine comprising: providing measurement values from first the “parameter of a pre-semiconductor manufacturing process”, second the “parameter of the semiconductor manufacturing process”, and third the “operation parameter of the semiconductor manufacturing process”; performing a fuzzy control to define two inputs and one output corresponding to the measurement values, wherein the difference between the first and third values, and the difference between the second and third values, forms the two inputs, then from the two inputs one target output is calculated by fuzzy inference; finally, determining if the target output is in or out of an acceptable range. Whereby the target output is the “machine control parameter of the semiconductor manufacturing process” and when within an acceptable range is used for adjusting the semiconductor machine.Type: GrantFiled: September 30, 2008Date of Patent: August 30, 2011Assignee: Inotera Memories, Inc.Inventors: Yi Feng Lee, Tzu-Cheng Lin, Chun Chi Chen, Yun-Zong Tian
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Publication number: 20110153660Abstract: A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor proType: ApplicationFiled: March 4, 2011Publication date: June 23, 2011Applicant: INOTERA MEMORIES, INC.Inventors: YIJ CHIEH CHU, CHUN CHI CHEN, YUN-ZONG TIAN, CHENG-HAO CHEN
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Publication number: 20110137595Abstract: A yield loss prediction method includes: performing a plurality of types of defect inspections upon a plurality of batches of wafers which begin to be processed during different periods to generate defect inspection data, respectively; for a specific batch of wafers different from the plurality of batches of wafers, calculating defect prediction data of at least one type of defect inspection according to the defect inspection data of at least the type of defect inspections; and predicting a yield loss of the specific batch of wafers according to at least the defect prediction data.Type: ApplicationFiled: March 16, 2010Publication date: June 9, 2011Inventors: Yij-Chieh Chu, Yun-Zong Tian, Shih-Chang Kao, Wei-Jun Chen, Cheng-Hao Chen
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Publication number: 20110112999Abstract: A method for predicting and warning of WAT value includes the steps as follows. A key process is selected and a WAT value after finishing the key process is used as a predictive goal. A predicting model is built. One batch or plural batches of predictive wafers are prepared, and a Fault Detection and Classification data (FDC data) and a metrology data from the predictive wafers of the key process are collected. The FDC data and the metrology data collected from the predictive wafers are inputted into the predicting model for processing a normal predicting procedure, and a predictive WAT value by the predicting model is outputted. The present invention can accurately predict the WAT value, effectively monitor some specific defective wafers and continuously perform the improvement for the specific defective wafer.Type: ApplicationFiled: February 11, 2010Publication date: May 12, 2011Applicant: INOTERA MEMORIES, INC.Inventors: YI-FENG LEE, SHIH CHANG KAO, YUN-ZONG TIAN, WEI JUN CHEN
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Publication number: 20110093226Abstract: A fault detection and classification (FDC) method for wafer acceptance test (WAT) parameters includes the following steps. A plurality of fault detection and classification parameters is collected. A plurality of wafer acceptance test parameters that are corresponded by the fault detection and classification parameters is collected. The fault detection and classification parameters are grouped. A contingency table of the wafer acceptance test parameters corresponding to the fault detection and classification parameters is built. A probability model of the contingency table is built. Finally, a safety range of the probability model is determined.Type: ApplicationFiled: December 27, 2010Publication date: April 21, 2011Applicant: INOTERA MEMORIES, INC.Inventors: YIJ CHIEH-CHU, CHUN CHI CHEN, YUN-ZONG TIAN, CHENG-HAO CHEN