Abstract: A histogram statistics circuit and a multimedia processing system, where the multimedia processing system includes a memory, a histogram statistics circuit, and a processor. The memory is configured to store multimedia data. The histogram statistics circuit is configured to obtain the multimedia data from the memory and perform histogram statistics on the multimedia data, to generate a statistical result. The processor is configured to process the multimedia data based on the statistical result and a histogram application algorithm.

Abstract: Embodiments of the present invention disclose a histogram statistics circuit and a multimedia processing system. The multimedia processing system includes: a memory, a histogram statistics circuit, and a processor. The memory is configured to store multimedia data. The histogram statistics circuit is configured to: obtain the multimedia data from the memory, and perform histogram statistics on the multimedia data, to generate a statistical result. The processor is configured to process the multimedia data based on the statistical result and a histogram application algorithm. In the present invention, the histogram statistics circuit can complete calculation of a plurality of pixels in parallel, and the multimedia data is properly grouped to reduce some ineffective operations. Therefore, computing efficiency of the multimedia processing system is greatly improved, and a requirement on real-time quality in a scenario such as facial recognition can be met.

Abstract: A vector permutation circuit and a vector processor are provided. The vector permutation circuit includes a grouping unit, m selection units connected to the grouping unit, j switching units connected to the m selection units, and a control unit connected to each selection unit and each switching unit, where each switching unit is connected to m/j selection units; the grouping unit divides to-be-permutated vector data into n vector data groups and output the n vector data groups to the m selection units; under control of the control unit, each selection unit selects a second vector data group from an input first vector data group, and outputs the second vector data group to a switching unit connected to the selection unit; under control of the control unit, each switching unit switches and outputs elements in the input second vector data group.

Abstract: A vector permutation circuit and a vector processor are provided. The vector permutation circuit includes a grouping unit, m selection units connected to the grouping unit, j switching units connected to the m selection units, and a control unit connected to each selection unit and each switching unit, where each switching unit is connected to m/j selection units; the grouping unit divides to-be-permutated vector data into n vector data groups and output the n vector data groups to the m selection units; under control of the control unit, each selection unit selects a second vector data group from an input first vector data group, and outputs the second vector data group to a switching unit connected to the selection unit; under control of the control unit, each switching unit switches and outputs elements in the input second vector data group.