Abstract: A semiconductor device includes an N-type semiconductor substrate, a drift layer, a semiconductor layer, a first trench located in the semiconductor layer, a gate located in the first trench, a P-well, a source region, and an N-type second semiconductor region that are located in the semiconductor layer, a source, and a drain. The drift layer includes an N-type column region and a P-type column region that are disposed in parallel and alternately. In the semiconductor device, an electrode is further disposed below the gate, a P-type first semiconductor region is disposed at the bottom of the first trench, the first semiconductor region is in contact with the electrode and the P-type column region located below the gate, and the electrode is electrically connected to the source.

Abstract: This application provides a power semiconductor device, which includes: a semiconductor substrate, where the semiconductor substrate is doped with a first-type impurity; an epitaxial layer, that is doped with the first-type impurity, the epitaxial layer is disposed on a surface of the semiconductor substrate, a first doped region doped with a second-type impurity is disposed on a first surface that is of the epitaxial layer and that is away from the semiconductor substrate, and a circumferential edge of the first surface of the epitaxial layer has a scribing region; a first metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate, where the first metal layer is electrically connected to the epitaxial layer; a second metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate; and a passivation layer.

Abstract: This application provides a power semiconductor device, which includes: a semiconductor substrate, where the semiconductor substrate is doped with a first-type impurity; an epitaxial layer, that is doped with the first-type impurity, the epitaxial layer is disposed on a surface of the semiconductor substrate, a first doped region doped with a second-type impurity is disposed on a first surface that is of the epitaxial layer and that is away from the semiconductor substrate, and a circumferential edge of the first surface of the epitaxial layer has a scribing region; a first metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate, where the first metal layer is electrically connected to the epitaxial layer; a second metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate; and a passivation layer.

Abstract: A silicon carbide MOSFET device is disclosed. The silicon carbide MOSFET device includes a gate oxide layer which is constituted by a first gate oxide layer and a second gate oxide layer. A thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer. Through dividing the gate oxide layer into two parts with different thicknesses, i.e., enabling the gate oxide layer to have a staircase shape, an electric field strength of the gate oxide layer can be effectively reduced, while a threshold voltage and a gate control property of the device are not affected. An on-resistance of the device can be reduced through increasing a width of a JFET region. A method for manufacturing the silicon carbide MOSFET device is further disclosed.

Abstract: A silicon carbide MOSFET device is disclosed. The silicon carbide MOSFET device includes a gate oxide layer which is constituted by a first gate oxide layer and a second gate oxide layer. A thickness of the second gate oxide layer is larger than a thickness of the first gate oxide layer. Through dividing the gate oxide layer into two parts with different thicknesses, i.e., enabling the gate oxide layer to have a staircase shape, an electric field strength of the gate oxide layer can be effectively reduced, while a threshold voltage and a gate control property of the device are not affected. An on-resistance of the device can be reduced through increasing a width of a JFET region. A method for manufacturing the silicon carbide MOSFET device is further disclosed.