Abstract: An interface circuit includes a phase inverter. An input end of the phase inverter is connected to a signal output end of a first power domain circuit, and an output end of the phase inverter is connected to a signal input end of a second power domain circuit. A power end of the phase inverter is connected to a power supply of the first power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the second power domain circuit. Alternatively, a power end of the phase inverter is connected to a power supply of the second power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the first power domain circuit.

Abstract: An interface circuit includes a phase inverter. An input end of the phase inverter is connected to a signal output end of a first power domain circuit, and an output end of the phase inverter is connected to a signal input end of a second power domain circuit. A power end of the phase inverter is connected to a power supply of the first power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the second power domain circuit. Alternatively, a power end of the phase inverter is connected to a power supply of the second power domain circuit, and a ground end of the phase inverter is connected to a reference ground of the first power domain circuit.

Abstract: A PWM circuit comprises: a charge and discharge circuit to receive a initial signal and, according to the initial signal, increase a voltage at an output end of thereof linearly or decrease the voltage; a comparator with a positive input end to receive a control signal and a negative input end connected to the output end of the charge and discharge circuit; a voltage transmission circuit with a first input end to receive the initial signal and a second input end to receive an output of the comparator, the voltage transmission circuit is configured to transmit the initial signal to an output end of the voltage transmission circuit when the output of the comparator is digital 1, and output digital 0 when the output of the comparator is digital 0.

Abstract: A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

Abstract: A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

Abstract: A PWM circuit comprises: a charge and discharge circuit to receive a initial signal and, according to the initial signal, increase a voltage at an output end of thereof linearly or decrease the voltage; a comparator with a positive input end to receive a control signal and a negative input end connected to the output end of the charge and discharge circuit; a voltage transmission circuit with a first input end to receive the initial signal and a second input end to receive an output of the comparator, the voltage transmission circuit is configured to transmit the initial signal to an output end of the voltage transmission circuit when the output of the comparator is digital 1, and output digital 0 when the output of the comparator is digital 0.