Abstract: Methods for isolating two adjacent transistors are disclosed. A substrate has a first semiconducting fin on a first region and a second semiconducting fin on a second region, and the first semiconducting fin and the second semiconducting fin contact each other at a jog region. A dummy gate within or adjacent the jog region is removed to expose a portion of the first semiconducting fin and form an isolation volume. Etching is performed to remove the exposed portion of the first semiconducting fin and create a trench in the substrate. The trench and the isolation volume are filled with at least one dielectric material to form an electrically isolating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrically conductive material to form two adjacent transistors electrically isolated from each other.

Abstract: Continuous polysilicon on oxide diffusion edge (CPODE) processes are described herein in which one or more semiconductor device parameters are tuned to reduce the likelihood of etching of source/drain regions on opposing sides of CPODE structures formed in a semiconductor device, to reduce the likelihood of depth loading in the semiconductor device, and/or to reduce the likelihood of gate deformation in the semiconductor device, among other examples. Thus, the CPODE processes described herein may reduce the likelihood of epitaxial damage to the source/drain regions, may reduce current leakage between the source/drain regions, and/or may reduce the likelihood of threshold voltage shifting for transistors of the semiconductor device. The reduced likelihood of threshold voltage shifting may provide more uniform and/or faster switching speeds for the transistors, more uniform and/or lower power consumption for the transistors, and/or increased device performance for the transistors, among other examples.

Abstract: Provided are semiconductor devices and methods for fabricating such devices. An exemplary method includes forming a fin structure over a semiconductor material; forming a sacrificial layer over the semiconductor material; removing a portion of the fin structure and an overlying portion of the sacrificial layer located over the portion of the fin structure to form a trench; forming an insulation structure in the trench, wherein an adjacent portion of the sacrificial layer is adjacent an end wall of the insulation structure; removing the adjacent portion to form a cavity partially defined by the end wall; lining the cavity with a liner, wherein an end portion of the liner is located on the end wall of the insulation structure; filling the cavity with a fill material; removing the end portion of the liner to form an opening; and forming an end isolation structure in the opening.

Abstract: Methods for fabricating semiconductor devices are provided. An exemplary method includes forming fins in a dense region and in an isolated region of a semiconductor substrate; performing a plasma dry etch process to remove a portion of at least one selected fin to form a first trench in the dense region and to remove a portion of at least one selected fin in the isolated region to form a second trench in the isolated region, wherein the plasma dry etch process includes: performing a passivation-oriented process and an etchant-oriented process; and controlling the passivation-oriented process and the etchant-oriented process to form the first trench with a desired first critical dimension and first depth and to form the second trench with a desired second critical dimension and second depth.

Abstract: Devices with metal structures formed with seams and methods of fabrication are provided. An exemplary method includes forming a metal plug having a top surface formed with a seam; depositing a film over the top surface of the metal plug and at least partially filling the seam; and etching the film from over the metal plug, wherein the film remains in the seam.

Abstract: Provided are semiconductor devices with isolation structures and methods for fabricating such devices. An exemplary method includes forming an isolation layer over a semiconductor material; forming source/drain regions over the isolation layer; removing a selected gate structure, wherein removing the selected gate structure forms a trench in the semiconductor material; and forming an isolation structure in the trench.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a first fin and around first channel regions that are disposed over the first fin; forming an interlayer dielectric (ILD) layer over the first fin around the dummy gate structure; replacing the dummy gate structure with a gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the first fin, where the first and second dielectric plugs cut the gate structure into a plurality of segments separated from each other; removing a segment of the gate structure interposed between the first dielectric plug and the second dielectric plugs to expose the first channel regions; removing the exposed first channel regions, where after removing the exposed first channel regions, a recess is formed in the ILD layer; and filling the recess with a dielectric material.

Abstract: A method of overlay measurement of a semiconductor structure includes a number of operations. A semiconductor structure with a pre-layer and a current layer over the pre-layer is provided, wherein the pre-layer includes a first overlay mark with a first grating group and a second grating group, and the current layer includes a second overlay mark. A semiconductor process is performed on the semiconductor structure. A detection beam is irradiated to the first overlay mark. A first intensity distribution of the first grating group and a second intensity distribution of the second grating group with respect to the reference point of the first overlay mark are received.

Abstract: The present invention provides a core-shell cathode characterized by comprising: a shell comprising an electrically conductive, porous carbon material; and a core, which is an inner cavity enclosed within the shell, wherein the core contains an active material and an electrolyte, and the active material comprises liquid polysulfide having the general formula Li2Sx, wherein 4?x?8; the shell comprises a first layer, an O-ring and a second layer sequentially stacked from bottom to top to form the inner cavity to contain the active material and the electrolyte. The present invention also provides a lithium-sulfur battery using said core-shell cathode, which attains both high sulfur loading and high sulfur content, and simultaneously satisfies high energy density, high capacity retention and high cycle stability under lean-electrolyte condition.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: A semiconductor structure includes a substrate, a multi-gate FET device disposed over the substrate, a first isolation disposed in the substrate, and a second isolation disposed in the substrate. The multi-gate FET device includes a gate structure and epitaxial source/drain structures disposed at two sides of the gate structure. The first isolation includes a first portion and a second portion over the first portion. A top surface of the second portion is aligned with a top surface of the epitaxial source/drain structures. A width of the second portion is different from a width of the first portion.

Abstract: A method for forming a semiconductor device structure includes forming first nanostructures and second nanostructures over a substrate. The method also includes forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures. The method also includes etching back the first metal gate layer over the first nanostructures and the second nanostructures. The method also includes removing the first metal gate layer over the second nanostructures. The method also includes forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.

Abstract: Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.

Abstract: A novel yellow phosphor of a fluorosulfide having a chemical formula of (A1-x-yCexBy)2Ca1-zSrzF4S2 and a tetragonal crystal phase is disclosed, wherein A and B are different rare earth metals other than Ce, the values of x, y, z are 0<x?1, 0?y?1, and 0?z?1, respectively. A preparation method of the fluorosulfide and white-light emitting diode application thereof are also disclosed.

Abstract: Novel red and green fluorosulfide phosphors have a chemical formula of (A1-x-yCexBy)SF, wherein A and B are both trivalent metal ions, 0<x?0.1, and 0?y?1. A is a rare earth metal, B is a rare earth metal or a group 13 metal. A preparation method of the fluorosulfide and white-light emitting diode application thereof are also disclosed.

Abstract: Novel red and green fluorosulfide phosphors have a chemical formula of (A1-x-yCexBy)SF, wherein A and B are both trivalent metal ions, 0<x?0.1, and 0?y?1. A is a rare earth metal, B is a rare earth metal or a group 13 metal. A preparation method of the fluorosulfide and white-light emitting diode application thereof are also disclosed.

Abstract: A novel yellow phosphor of a fluorosulfide having a chemical formula of (A1-x-yCexBy)2Ce1-zSr2F4S2 and a tetragonal crystal phase is disclosed, wherein A and B are different rare earth metals other than Ce, the values of x, y, z are 0<x?1, 0?y?1, and 0?z?1, respectively. A preparation method of the fluorosulfide and white-light emitting diode application thereof are also disclosed.

Abstract: Novel red and green fluorosulfide phosphors have a chemical formula of (A1-x-yCexBy)SF, wherein A and B are both trivalent metal ions, 0<x?0.1, and 0?y?1. A is a rare earth metal, B is a rare earth metal or a group 13 metal. A preparation method of the fluorosulfide and white-light emitting diode application thereof are also disclosed.

Abstract: A carbonitride phosphor is provided, which is represented by a general chemical formula of (M1-x-yNxCey)2(CN2)3, in which 0.005?x?0.20, 0.005?y?0.15, and M and N are respectively selected from a group consisting of yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium and cassiopeium.