Abstract: The present disclosure provides a three-dimensional memory device and a method of fabricating the same, which includes a substrate, and a memory stack structure. The memory stack structure is disposed on the substrate, and includes a plurality of stack units sequentially stacked into a staircase shape, wherein each of the stack units has a stepped slope, the stepped slope of any one of the stack units disposed in a related lower position is less than the stepped slope of another one of the stack units disposed over the one of the stack units. Through this arrangements, the three-dimensional memory device may therefore obtain an optimized structural integrity, as well as improved component efficiency.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A three-dimensional memory device includes a staircase structure comprising steps respectively comprising a conductive layers and a dielectric layer. A sidewall of the conductive layer is recessed from a sidewall of the dielectric layer to form a recess that exposes a portion of a bottom surface of the dielectric layer.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A DRAM includes a substrate, a plurality of first active regions disposed on the substrate and arranged end-to-end along the first direction, and a plurality of second active regions disposed between the first active regions and arranged end-to-end along the first direction. The second active regions respectively have a first sidewall adjacent to a first trench between the second active region and one of the first active regions and a second sidewall adjacent to a second trench between the ends of the first active regions, wherein the second sidewall is taper than the first sidewall in a cross-sectional view.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.