Abstract: The embodiments of the present disclosure disclose gaze estimation cross-scene adaptation method and device based on outlier guidance. A specific implementation of the method comprises: performing pre-training on a source domain based on a given arbitrary gaze estimation model, to obtain a collaborative learning model group; determining an average collaborative model corresponding to each collaborative learning model in the collaborative learning model group, to obtain an average collaborative model group; generating an outlier corresponding to the collaborative learning model group based on a target image, the collaborative learning model group and the average collaborative model group; using an outlier loss function and the outlier to optimize the collaborative learning model group; using any collaborative learning model in the optimized collaborative learning model group to perform gaze estimation.

Abstract: The present application provides a detecting method of an operating state of a power supply and a detecting apparatus, where the power supply includes a primary circuit, a transformer and a secondary circuit. The secondary circuit includes a secondary current detecting unit, a temperature detecting unit and a secondary controlling unit. Firstly the secondary current detecting unit detects a current value of the secondary circuit, then the secondary controlling unit compares the current value of the secondary circuit with a preset current threshold. When the current value of the secondary circuit is less than or equal to the preset current threshold, the temperature detecting unit detects a temperature value of the power supply and the secondary controlling unit determines the operating state of the power supply according to the acquired temperature value of the power supply.

Abstract: The embodiments of this disclosure disclose an image anomaly detection method. A specific implementation of the method comprises: obtaining a test image; inputting the test image to an autoencoder to obtain a first reconstructed image; inputting the first reconstructed image to an expert network to obtain a second reconstructed image; based on the test image, the first reconstructed image, the second reconstructed image and a perceptual measurement method, generating an anomaly score matrix; based on the anomaly score matrix, generating anomalous area information. This implementation achieves a zero-shot training network and improves the accuracy of locating anomalous areas.

Abstract: The embodiments of this disclosure disclose an unsupervised image-to-image translation method. A specific implementation of this method comprises: obtaining an initial image, and zooming the initial image to a specific size; performing spatial feature extraction on the initial image to obtain feature information; inputting the feature information to a style-content separation module to obtain content feature information and style feature information; generating reference style feature information of a reference image in response to obtaining the reference image, and setting the reference style feature information as a Gaussian noise in response to not obtaining the reference image; inputting the content feature information and the reference style feature information into a generator to obtain a target image; and zooming the target image to obtain a final target image. This implementation can be applied to a variety of different high-level visual tasks, and improve the expandability of the whole system.

Abstract: The embodiments of the present disclosure relate to the field of display technology, and in particular to a display substrate, a display panel, and a display device. The display substrate includes a first electrode, a first wire, and a second wire; the first electrode is provided with a plurality of slits; the first wire is provided on a side of the first electrode, and a first gap is provided between the first wire and the first electrode, and the first wire being electrically connected to the first electrode; a second wire provided on a side of the first electrode away from the first wire, and a second gap being provided between the second wire and the first electrode; wherein each of the slits is provided with a first end and a second end opposed to each other, and the first end is close to the first wire, and the second end is close to the second wire, and a light-transmitting part of the first end is larger than a light-transmitting part of the second end.

Abstract: A device area and a marking area neighboring the device area over a dielectric stack are determined. The dielectric stack includes insulating material layers and sacrificial material layers arranged alternatingly over a substrate. The device area and the marking area are patterned using a same etching process to form a marking pattern having a central marking structure in a marking area and a staircase pattern in the device area. The marking pattern and the staircase pattern have a same thickness equal to a thickness of at least one insulating material layer and one sacrificial material layer, and the central marking structure divides the marking area into a first marking sub-area farther from the device area and a second marking sub-area closer to the device area. A first pattern density of the first marking sub-area is greater than or equal to a second pattern density of the second marking sub-area.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having insulating layers and conductor layers arranged alternatingly over a substrate along a vertical direction; and a marking pattern having interleaved layers over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area. The central marking structure consists of interleaved layers and divides the marking area into a first marking sub-area and a second marking sub-area. A first pattern density of the first marking sub-area is higher than or equal to a second pattern density of the second marking sub-area.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

Abstract: A shift register unit, a method of driving a shift register unit, a gate driving circuit, and a display device are disclosed. The shift register unit includes an input circuit and an output circuit. The input circuit is configured to write an input signal of the input terminal to the first node in response to an input control signal, so as to control a level of the first node. The output circuit is configured to receive a clock signal of the clock signal terminal and output a scanning signal through the pixel signal output terminal under control of the level of the first node. The output circuit includes a variable resistor, and the variable resistor is configured to adjust a level of the scanning signal according to a resistance value of the variable resistor.

Abstract: A method for controlling a subsidence area caused by underground mining in an adjoining open-pit mine, applied in an open-pit and underground coordinated mining process. In the method, a ground subsidence area caused by underground mining and production is directly filled and covered with overburden materials such as soil and rock discharged from an adjoining open-pit mine; small and medium fracture zones and large fracture zones caused by mining are timely backfilled, tamped, and levelled according to areas before the ground subsidence area appears, the thickness of the levelled soil layer is kept above 1 m, and the area slope is controlled within 7°.

Abstract: A shift register unit, a method of driving a shift register unit, a gate driving circuit, and a display device are disclosed. The shift register unit includes an input circuit and an output circuit. The input circuit is configured to write an input signal of the input terminal to the first node in response to an input control signal, so as to control a level of the first node. The output circuit is configured to receive a clock signal of the clock signal terminal and output a scanning signal through the pixel signal output terminal under control of the level of the first node. The output circuit includes a variable resistor, and the variable resistor is configured to adjust a level of the scanning signal according to a resistance value of the variable resistor.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a marking pattern for controlling a trimming rate of a photoresist trimming process includes a plurality of interleaved layers, the plurality of interleaved layers including at least two layers of different materials stacking along a vertical direction over a substrate. In some embodiments, the marking pattern also includes a central marking structure that divides the marking area into a first marking sub-area farther from a device area and a second marking sub-area closer to the device area, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

Abstract: Embodiments of a marking pattern in forming the staircase structure of a three-dimensional (3D) memory device are provided. In an example, a semiconductor device includes a stack structure having a plurality of insulating layers and a plurality of conductor layers arranged alternatingly over a substrate along a vertical direction. In some embodiments, the semiconductor device also includes a marking pattern having a plurality of interleaved layers of different materials over the substrate and neighboring the stack structure. The marking pattern includes a central marking structure located in a marking area, the central marking structure dividing the marking area into a first marking sub-area farther from the stack structure and a second marking sub-area closer to the stack structure, a first pattern density of the first marking sub-area being higher than or equal to a second pattern density of the second marking sub-area.

Abstract: A gate driving unit circuit pair and a driving method thereof, a gate driving circuit and a display device are provided. The gate driving unit circuit pair includes two gate driving unit circuits, each of which includes a first output sub-circuit, a second output sub-circuit, and a coupling and isolation sub-circuit. The coupling and isolation sub-circuit is configured to: if the first output sub-circuit outputs signal, isolate the signal of the first output terminal from the signal of the second output terminal; or else, couple the signal of the first output terminal to the second output terminal.

Abstract: A method for controlling a subsidence area caused by underground mining in an adjoining open-pit mine, applied in an open-pit and underground coordinated mining process. In the method, a ground subsidence area caused by underground mining and production is directly filled and covered with overburden materials such as soil and rock discharged from an adjoining open-pit mine; small and medium fracture zones and large fracture zones caused by mining are timely backfilled, tamped, and levelled according to areas before the ground subsidence area appears, the thickness of the levelled soil layer is kept above 1 m, and the area slope is controlled within 7°.

Abstract: A gate driving unit circuit pair and a driving method thereof, a gate driving circuit and a display device are provided. The gate driving unit circuit pair includes two gate driving unit circuits, each of which includes a first output sub-circuit, a second output sub-circuit, and a coupling and isolation sub-circuit. The coupling and isolation sub-circuit is configured to: if the first output sub-circuit outputs signal, isolate the signal of the first output terminal from the signal of the second output terminal; or else, couple the signal of the first output terminal to the second output terminal.

Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.

Abstract: There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l.

Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.

Abstract: There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer on the fin; d. forming a shallow trench isolation on both sides of the fin; e. forming a sacrificial gate stack and a spacer on the top surface and sidewalls of the channel region which is in the middle of the fin; f. forming source/drain regions in both ends of the fin; g. depositing an interlayer dielectric layer on the sacrificial gate stack and the source/drain regions, planarizing later to expose the sacrificial gate stack; h. removing the sacrificial gate stack stack to form a sacrificial gate vacancy and expose the channel region and the channel protective layer; i. covering a portion of the semiconductor structure in one end of the fin with a photoresist layer; j. removing a portion of the spacer not covered; k. removing the photoresist layer and filling a gate stack in the sacrificial gate vacancy; l.