Patents by Inventor Yunfeng Bian

Yunfeng Bian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230088467
    Abstract: An audio processing method includes: obtaining relative attitude information between a lens and a plurality of microphones, where the lens is movable relative to at least one of the plurality of microphones; obtaining original audio signals acquired by the plurality of microphones; determining weight information corresponding to the original audio signals based on the relative attitude information; and synthesizing the original audio signals based on the weight information to obtain a target audio signal, where the target audio signal is played with images captured by the lens. The method disclosed in this application resolves a problem that a sound source orientation indicated by recorded audio does not match the images captured by the lens.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 23, 2023
    Applicant: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Yang LIU, Pinxi MO, Yunfeng BIAN, Zheng XUE
  • Publication number: 20220321492
    Abstract: This application relates to the field of data communication, and in particular, to a packet buffering method, an integrated circuit system, and a storage medium. The method can improve utilization of the on-chip buffer. The packet buffering method may be applied to a network device. The network device includes a first storage medium and a second storage medium. The first storage medium is a local buffer, and the second storage medium is an external buffer. The method may include: receiving a first packet, and identifying a queue number of the first packet, where the queue number indicates a queue for storing the first packet; querying a queue latency based on the queue number; determining a first latency threshold based on usage of the first storage medium; and buffering the first packet in the first storage medium or the second storage medium based on the queue latency and the first latency threshold.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 6, 2022
    Inventors: Hua WEI, Yunfeng BIAN, Xiaozhong WANG
  • Patent number: 8325603
    Abstract: A method and apparatus for dequeuing data are disclosed. The method includes: obtaining storage addresses of packets in each queue, and dequeuing, by multiple dequeue processing engines, the packets in each queue in parallel according to the storage addresses of the packets in each queue. Multiple dequeue processing engines dequeue the packets in multiple queues in parallel, and thus the data dequeue efficiency and performance are improved.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: December 4, 2012
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yunfeng Bian, Haiyan Luo, Bai Cheng, Youjie Duan, Hui Lu
  • Patent number: 8291167
    Abstract: A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to cache received write requests and write data associated with the write requests and sort the write requests; a request judging device, configured to extract the sorted write requests and the write data associated with the write requests according to write time sequence restriction information of an off-chip memory device; and an off-chip memory device controller, configured to write the write data extracted by the request judging device in the off-chip memory device.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: October 16, 2012
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Qin Zheng, Haiyan Luo, Hui Lu, Junliang Lin, Yunfeng Bian
  • Publication number: 20110002345
    Abstract: A method and apparatus for dequeuing data are disclosed. The method includes: obtaining storage addresses of packets in each queue, and dequeuing, by multiple dequeue processing engines, the packets in each queue in parallel according to the storage addresses of the packets in each queue. Multiple dequeue processing engines dequeue the packets in multiple queues in parallel, and thus the data dequeue efficiency and performance are improved.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 6, 2011
    Inventors: Yunfeng Bian, Haiyan Luo, Bai Cheng, Youjie Duan, Hui Lu
  • Publication number: 20100332743
    Abstract: A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to cache received write requests and write data associated with the write requests and sort the write requests; a request judging device, configured to extract the sorted write requests and the write data associated with the write requests according to write time sequence restriction information of an off-chip memory device; and an off-chip memory device controller, configured to write the write data extracted by the request judging device in the off-chip memory device. With a combination of the on-chip and off-chip memory devices, a large-capacity data storage space and a high-speed read and write efficiency is achieved.
    Type: Application
    Filed: September 8, 2010
    Publication date: December 30, 2010
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Qin Zheng, Haiyan Luo, Hui Lu, Junliang Lin, Yunfeng Bian
  • Publication number: 20100220589
    Abstract: A method, an apparatus, and a system for processing buffered data are disclosed. The method includes: packing data packets in a same queue; splitting the packed data packet into multiple data cells according to a predetermined cell size; and storing the split data cells in multiple memories. The preceding method, apparatus, and system improve the read and write efficiency of the memories and improve the balance of the read and write bandwidths among multiple memories, thus improving the system performance.
    Type: Application
    Filed: May 13, 2010
    Publication date: September 2, 2010
    Inventors: Qin Zheng, Haiyan Luo, Yunfeng Bian, Hui Lu