Abstract: A method for optimizing computing power of a neural network module, a chip, an electronic device, and a medium are provided. The method includes: obtaining, by the chip, a computational graph of the neural network module having respective operators; performing at least one of adjustments below at least 1 time on a first operator in the computational graph according to specific operation of each operator: counterchanging a position of the first operator with a subsequent operator or a preceding operator in the computational graph, splitting the first operator into more than two identical operators, and inserting a plurality of first operators that are capable of canceling each other out; determining a second operator adjacent to the adjusted first operator in the computational graph according to the specific operations of each operator; and performing merge or cancellation, by the chip, on the adjusted first operator and the second operator.

Abstract: A processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates a vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading to-be-processed data. The target operand specifies a target storage location in the memory for writing a processed result. The processor further includes an arithmetic logic unit configured to: read the to-be-processed data from the source storage location of the memory; perform, on the to-be-processed data, an arithmetic logic operation associated with the vector operation specified by the target instruction; and write the processed result to the target storage location of the memory.

Abstract: According to an embodiment of the disclosure, a processor and a method, device and storage medium for data processing are provided. The processor includes a plurality of processor cores, each of the plurality of processor cores including a data cache for reading and writing data and an instruction cache for reading instructions, the instruction cache being separate from the data cache. The processor also includes a distributor communicatively coupled to the plurality of processor cores. The distributor is configured to distribute to-be-processed data to a respective data cache of at least one processor core of the plurality of processor core, and distribute instructions associated with the to-be-processed data to a respective instruction cache of the at least one processor core for processing.

Abstract: At least one embodiment of the present disclosure provides a data processing method and apparatus for a processor, a processor, an electronic device and a storage medium, and the processor includes at least one computing core. The data processing method includes: obtaining a configuration space for a target parameter; obtaining a computational time model of the processor, the computational time model is a function of the target parameter and number of computing cores of the processor; traversing the target parameter in the configuration space, and calculating, based on the computational time model, a computational time corresponding to the target parameter that is selected; in response to the target parameter being a k-th parameter with a minimum computational time, determining the target parameter as the k-th parameter; and using the k-th parameter to configure a computational size of each computing core in the at least one computing core.

Abstract: A convolution operation method, a convolution operation apparatus, an electronic device and a storage medium. The method includes: determining an operation convolution kernel, wherein the operation convolution kernel is obtained on the basis of an initial convolution kernel; adjusting an arrangement mode of input data on the basis of the number of channels of the operation convolution kernel, so as to obtain target data, wherein the size of the target data and the number of channels of the target data are different from the size of the input data and the number of channels of the input data, and the number of channels of the target data is equal to the number of channels of the operation convolution kernel; and performing a convolution operation on the basis of the target data and the operation convolution kernel, so as to obtain a convolution operation result.

Abstract: An intelligent layout design method of curvilinearly stiffened structure based on image feature learning. Firstly, the design variables of the curvilinearly stiffened structure are determined based on the path function. The autoencoder network is built to complete the learning of the structural characteristics of the image, and the transfer learning of the model is further carried out. The convolution neural network is built to complete the learning of the image set with mechanical response labels. Finally, the evolutionary algorithm is used to optimize the layout of the curvilinearly stiffened structure based on the model. The invention solves the problem that the traditional optimization method is difficult to deal with the optimization design with many and variable design variables, and is expected to become one of the most potential technical means involved in the layout design of components in the engineering field.

Abstract: Disclosed are systems and methods for network architecture that is a server-centric network architectural design.

Abstract: Disclosed are systems and methods for network architecture that is a server-centric network architectural design.

Abstract: Disclosed are systems and methods for network architecture that is a server-centric network architectural design.

Abstract: Disclosed are systems and methods for network architecture that is a server-centric network architectural design.

Abstract: Disclosed are systems and methods for network architecture that is a server-centric network architectural design.

Abstract: Disclosed are systems and methods for network architecture that is a server-centric network architectural design.

Abstract: A hybrid Butterfly Cube (“BCube”) architecture is described herein. The BCube architecture is a server-centric network architectural design, and includes a plurality of servers. Each of the plurality of servers may have multiple network ports and serve not only as an end host, but also an intermediate relay node for other servers. The BCube architecture further includes a plurality of switches which are arranged in multiple levels. Each switch has a certain number of network ports for connecting to the servers. The BCube architecture provides multiple parallel paths between any two servers. A packet source routing protocol and a BCube source routing (BSR) protocol are used to determine which path is used for routing a packet between any two servers.

Abstract: Disclosed are systems and methods for network architecture that is a server-centric network architectural design.