Abstract: Disclosed is a many-bit, groupable, reconfigurable, multi-valued, electronic operator and its construction method. Each bit of the electronic operator is provided with n column calculators and one potential combiner. A data input line is connected to an input terminal of an A signal selector, and an output terminal of the A signal selector is connected to a work permitter. Another input terminal of the work permitter is connected to a reconfiguration latch, and an output terminal of the work permitter is further connected to an output validator. Another input terminal of the output validator is connected to a power supply Vcc, and an output terminal of the output validator is connected to an output generator. Another input terminal of the output generator is connected to a reconfiguration circuit, and an output terminal of the output generator is connected to the potential combiner.

Abstract: Disclosed is a method for configuring an MSD parallel adder based on ternary logic operators. Five ternary logic operators that satisfy a sufficient condition for MSD addition are used to configure an MSD parallel adder. During the arrangement of a ternary logic operator, any method in the following may be used: each of ternary operators of n bits is reconfigured into a ternary logic operator each time, and reconfiguration is performed five times for implementation; each of ternary operators of n bits is reconfigured into two ternary logic operators having the same input each time, and reconfiguration is performed three times for implementation; each of ternary operators of n bits is reconfigured into five ternary logic operators of the same time, and reconfiguration is performed once for implementation; corresponding unreconfigurable ternary logic operators are used instead for the foregoing reconfiguration process.

Abstract: Disclosed is a many-bit, groupable, reconfigurable, multi-valued, electronic operator and its construction method. Each bit of the electronic operator is provided with n column calculators and one potential combiner. A data input line is connected to an input terminal of an A signal selector, and an output terminal of the A signal selector is connected to a work permitter. Another input terminal of the work permitter is connected to a reconfiguration latch, and an output terminal of the work permitter is further connected to an output validator. Another input terminal of the output validator is connected to a power supply Vcc, and an output terminal of the output validator is connected to an output generator. Another input terminal of the output generator is connected to a reconfiguration circuit, and an output terminal of the output generator is connected to the potential combiner.

Abstract: A computer system includes an addressing assembly, connected respectively to high bits of a memory address line of a processor and high bits of a word address line of a storage, and used to convert, in a preset continuous or discrete range on the storage, high bits of a memory address formed by the processor into high bits of a corresponding word address of the storage and output the high bits to the storage. Low bits of the memory address line of the processor are connected to low bits of the word address line of the storage. The preset range is smaller than or equal to an addressing range of the memory address line of the processor. The processor changes storage units of the storage covered by the preset range by changing the preset range. Thus it reduces cost, improves operation efficiency, shortens operation time, and has wide applicability.

Abstract: A computer system includes an addressing assembly, connected respectively to high bits of a memory address line of a processor and high bits of a word address line of a storage, and used to convert, in a preset continuous or discrete range on the storage, high bits of a memory address formed by the processor into high bits of a corresponding word address of the storage and output the high bits to the storage. Low bits of the memory address line of the processor are connected to low bits of the word address line of the storage. The preset range is smaller than or equal to an addressing range of the memory address line of the processor. The processor changes storage units of the storage covered by the preset range by changing the preset range. Thus it reduces cost, improves operation efficiency, shortens operation time, and has wide applicability.