Abstract: A new technique is provided to manufacture a CIS module by employing an alignment-plate, a light-guide plate, and a resolution plate. The above plates can be selected to be pre-fabricated into one piece to reduce the number of components for the CIS module. The dimension of resolution definition structures of resolution plate determines the resolution of CIS module and allows only the reflect light from the image with a desired resolution to pass through. Consequently, it alleviates the butting difficulty in the convention butting operation to form a linear sensor array. Also, a signal reading technique is provided to improve the photo-response of the conventional photo-sensing device. Therefore, operation speed is increased and product performance is improved.

Abstract: A sensor chip with an on-chip operational amplifier is described for the formation into a sensor array of a Contact Image Sensor (CIS) module. A number of extra on-chip bonding pads are provided which are electrically connected to the operational amplifier, the associated input resistor and the charge integration capacitor in a selective manner. A number of extra off-chip common conductor stripes are also provided on the substrate for the chip array. A set of wiring patterns are then used to selectively connect these on-chip bonding pads with their corresponding off-chip common conductor stripes resulting in a CIS module which provides both a variable gain of a selected single operational amplifier and an equivalent charge integration capacitance which is the summation of the capacitors from the individual sensor chips within the chip array. Additionally, the associated input resistors can be replaced with an MOS transistor whose control gate can be similarly programmed with the wiring pattern.

Abstract: A sensor chip with an on-chip operational amplifier is described for the formation into a sensor array of a Contact Image Sensor (CIS) module. A number of extra on-chip bonding pads are provided which are electrically connected to the operational amplifier, the associated input resistor and the charge integration capacitor in a selective manner. A number of extra off-chip common conductor stripes are also provided on the substrate for the chip array. A set of wiring patterns are then used to selectively connect these on-chip bonding pads with their corresponding off-chip common conductor stripes resulting in a CIS module which provides both a variable gain of a selected single operational amplifier and an equivalent charge integration capacitance which is the summation of the capacitors from the individual sensor chips within the chip array. Additionally, the associated input resistors can be replaced with an MOS transistor whose control gate can be similarly programmed with the wiring pattern.

Abstract: A SOI wafer is produced by employing a bonding tool set which can be repeatedly used to reduce manufacturing cost. The use of a bonding tool set enables its application in the fabrication of IC patterns on both sides of a thin semiconductor film. A new IC fabrication method called parallel process technique is developed to manufacture integrated circuits by utilizing a bonding tool set. This parallel process technique simplifies the complex IC chip fabrication in addition to the yield improvement and the reduction of cycle time.

Abstract: Proper operation of an integrated circuit (IC) is destroyed when voltage exceeding a predetermined level is applied to the circuit. A switching MOS transistor utilizing floating gate technology is used to shunt electrostatic discharge (ESD) away from the IC. The switching MOS transistor is adapted to switch at a voltage level which is greater than the normal operating voltage for the IC but less than the predetermined voltage level characteristic of the IC. A first switching MOS transistor provides a path for a positive ESD stress by having its control gate and drain connected to the line of interest and its source connected to a reference point. Thus, when a positive voltage spike greater than the circuit voltages occurs on the line of interest, the first switching MOS transistor shunts the ESD stress away from the line of interest.

Abstract: An integrated circuit fabrication process for improving step coverage of the metal lines and of metal layer interconnections is disclosed. A conductive polysilicon, polycide, or polycide-on-polysilicon plug is formed in contact apertures by successive silicidation sequences of silicon/refractory metal deposition and heat treatment. A preceding silicide may also be removed prior to a succeeding silicidation to reduce silicon lining.

Abstract: High quality silicon oxide is grown for integrated circuits by oxidizing poly-crystalline silicon under an oxygen gas flow. A diffusion stop layer of thermal silicon nitride is formed on the underlying substrate prior to the deposition of the poly layer to be oxidized. The nitride layer isolates the substrate from diffused oxygen within the poly layer during oxidation, permitting a non-critical, oxidation time. Extension of the oxidation period elimates extended imperfect or "loose" chemical bonds throughout the oxide layer formed. Corner stress common in trench applications is minimized because the nitride prevents oxidation in the substrate. The oxidation of undoped poly over doped poly proceeds conformally because the nitride layer therebetween inhibits the enhanced oxidation effect of impurities in the doped poly.

Abstract: The invention discloses an improved process to form a silicide layer on an integrated circuit structure. The conventional lateral silicide growth is prevented by employing a slot configuration which is formed with the self-aligned process. It is simple to construct a multilevel interconnect scheme with the practice of the invention.

Abstract: The invention discloses an improved process for forming one or more metal strips on an integrated circuit structure by wet etching of a metal layer which comprises forming an intermediate layer over the integrated circuit structure; forming slots in the intermediate layer; forming a metal layer over the intermediate layer; and wet etching the metal layer sufficiently to remove all metal in the slots while retaining metal on the intermediate layer between the slots to form the desired one or more metal strips. Multiple levels of metal strips may be formed in an integrated circuit structure using the method of the invention.