Patents by Inventor Yung-chen Chen
Yung-chen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991576Abstract: A method for handling a Random Access (RA) procedure in a Bandwidth Part (BWP) switching operation is provided. The method includes: receiving a configuration of a first BWP through Radio Resource Control (RRC) signaling from a Base Station (BS); initiating an RA procedure on the first BWP; receiving, during the RA procedure on the first BWP, Downlink Control Information (DCI) indicating a BWP switching from the first BWP to a second BWP; determining whether to switch to the second BWP in response to receiving the DCI; and in a case that the UE determines to switch to the second BWP: stopping the RA procedure that is ongoing on the first BWP; determining, after stopping the RA procedure, whether the second BWP is configured with an RA resource; and initiating, after determining that the second BWP is not configured with the RA resource, a new RA procedure on an initial BWP.Type: GrantFiled: September 30, 2022Date of Patent: May 21, 2024Assignee: FG Innovation Company LimitedInventors: Hung-Chen Chen, Chie-Ming Chou, Chia-Hung Wei, Yung-Lan Tseng
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Publication number: 20240157412Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.Type: ApplicationFiled: January 26, 2024Publication date: May 16, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bo Chen CHEN, Sheng-Wei Wu, Yung-Li Tsai
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Patent number: 11979854Abstract: A method for monitoring paging is provided. The method is performed by a user equipment (UE) and includes actions of receiving a first Physical Downlink Control Channel (PDCCH) addressed to a first Radio Network Temporary Identifier (RNTI), and stopping monitoring a second PDCCH addressed to a second RNTI if the first PDCCH includes a paging stop indicator, where the second RNTI is the same as the first RNTI.Type: GrantFiled: December 1, 2021Date of Patent: May 7, 2024Assignee: FG Innovation Company LimitedInventors: Mei-Ju Shih, Hung-Chen Chen, Yung-Lan Tseng, Chie-Ming Chou
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Patent number: 11979780Abstract: A method for requesting a target system information block (SIB) associated with a target service is provided. The method initiates a dedicated SIB request procedure to send, to a serving cell, a request for the target SIB. The method initiates the dedicated SIB request procedure while the UE has stored at least one SIB segment of a plurality of SIB segments associated with the target SIB, and before the target SIB is successfully assembled based on the plurality of SIB segments. The method transmits, to the serving cell, the request for the target SIB to the serving cell and upon the transmission of the request starts a timer, where a second dedicated SIB request procedure is not allowed to be initiated while the timer is running.Type: GrantFiled: July 8, 2021Date of Patent: May 7, 2024Assignee: FG Innovation Company LimitedInventors: Yung-Lan Tseng, Hung-Chen Chen, Mei-Ju Shih
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Patent number: 11974356Abstract: The embodiments of the disclosure provide a method for maintaining multi-SIM (Subscriber Identity Module) configuration and user equipment (UE). The method includes: receiving, by the UE, a first multi-SIM support information from a first cell, wherein the first multi-SIM support information is generated and transmitted from a second cell to the first cell via an inter-node signaling from the second cell to the first cell, and the first cell and the second cell belong to a first network; transmitting, by the UE, a multi-SIM assistance information message to the second cell, wherein the multi-SIM assistance information message is determined based on the first multi-SIM support information.Type: GrantFiled: December 28, 2021Date of Patent: April 30, 2024Assignee: FG Innovation Company LimitedInventors: Yung-Lan Tseng, Mei-Ju Shih, Hung-Chen Chen
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Patent number: 11958090Abstract: The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.Type: GrantFiled: July 28, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo Chen Chen, Sheng-Wei Wu, Yung-Li Tsai
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Publication number: 20240098833Abstract: A method for mobility enhancement in wireless communication systems is provided. The method is performed by a User Equipment (UE) configured with a first Small Data Transmission (SDT) configuration by a first cell. The method includes receiving a Radio Resource Control (RRC) release message including a suspend configuration from the first cell; transitioning to an RRC INACTIVE state in response to receiving the RRC release message; receiving, in the RRC INACTIVE state, a System Information Block Type 1 (SIB1) including a second SDT configuration from a second cell; camping on the second cell in response to receiving the SIB1 from the second cell; and while the UE is camping on the second cell, refraining from using the first SDT configuration to initiate an SDT procedure associated with the second cell in a case that the UE does not support performing the SDT procedure associated with the second cell.Type: ApplicationFiled: September 14, 2023Publication date: March 21, 2024Inventors: YUNG-LAN TSENG, YEN-HUA LI, HAI-HAN WANG, HUNG-CHEN CHEN
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Patent number: 11937327Abstract: A user equipment (UE) and a method performed by the UE are provided. The method includes transitioning from a radio resource control (RRC) inactive (RRC_INACTIVE) state to an RRC idle (RRC_IDLE) state upon determining that the UE has failed to find a suitable cell and camped on an acceptable cell; and discarding a radio access network (RAN) notification area (RNA) configuration that comprises at least one of a list of tracking area identities (IDs) or a list of RAN area IDs in response to the transitioning from the RRC_INACTIVE state to the RRC_IDLE state. The acceptable cell fulfills a minimum set of requirements to initiate an emergency call and to receive one or more Earthquake & Tsunami Warning System (ETWS) and Commercial Mobile Alert System (CMAS) notifications. The suitable cell provides normal services. The acceptable cell provides limited services.Type: GrantFiled: July 29, 2022Date of Patent: March 19, 2024Assignee: FG Innovation Company LimitedInventors: Mei-Ju Shih, Yung-Lan Tseng, Hung-Chen Chen, Chie-Ming Chou
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Patent number: 11924698Abstract: A method for a user equipment (UE) for cell selection while the UE is in a radio resource control (RRC) Inactive state is provided. The method receives, via control signaling, a configuration indicating a target frequency carrier and a corresponding target core network (CN) type. The method then causes the UE to transition from an RRC Connected state to the RRC Inactive state based on the received configuration. While the UE is in the RRC Inactive state, the method selects a suitable cell among a plurality of suitable cells that are associated with the target frequency carrier. The method selects the suitable cell irrespective of the received target CN type.Type: GrantFiled: June 28, 2022Date of Patent: March 5, 2024Assignee: FG Innovation Company LimitedInventors: Yung-Lan Tseng, Mei-Ju Shih, Hung-Chen Chen
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Patent number: 11917445Abstract: A method performed by a BS for CHO is provided. The method includes transmitting a CHO command to a UE, the CHO command including a CHO command ID and a measurement ID associated with the CHO command ID; causing the UE to execute the CHO command to handover to a target BS when a trigger condition associated with the measurement ID is fulfilled; causing the UE to forgo transmitting the measurement report during the execution of the CHO command despite the UE being configured, via a report configuration associated with the measurement ID, to transmit the measurement report; transmitting, to the UE, a message that causes the UE to remove the CHO command; and after transmitting the message to the UE, determining that the report configuration is removed by the UE without transmitting, to the UE, an instruction to remove the report configuration.Type: GrantFiled: May 19, 2022Date of Patent: February 27, 2024Assignee: FG Innovation Company LimitedInventors: Hung-Chen Chen, Yung-Lan Tseng, Mei-Ju Shih, Chie-Ming Chou
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Publication number: 20230387893Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.Type: ApplicationFiled: July 31, 2023Publication date: November 30, 2023Inventors: Seid Hadi RASOULI, Jerry Chang Jui KAO, Xiangdong CHEN, Tzu-Ying LIN, Yung-Chen CHEN, Hui-Zhong ZHUANG, Chi-Lin LIU
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Publication number: 20230110352Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Inventors: Seid Hadi RASOULI, Jerry Chang Jui KAO, Xiangdong CHEN, Tzu-Ying LIN, Yung-Chen CHEN, Hui-Zhong ZHUANG, Chi-Lin LIU
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Patent number: 11545965Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.Type: GrantFiled: November 11, 2020Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chen, Hui-Zhong Zhuang, Chi-Lin Liu
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Publication number: 20210226615Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.Type: ApplicationFiled: November 11, 2020Publication date: July 22, 2021Inventors: Hadi RASOULI, Jerry Chang Jui KAO, Xiangdong CHEN, Tzu-Ying LIN, Yung-Chen CHEN, Hui-Zhong ZHUANG, Chi-Lin LIU
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Patent number: 6935405Abstract: A sink compound laminate molding process having a copper material in thickness of 0.1-0.8 mm placed at the bottom of the molding cavity with the bottom of the copper laminate fully bound to the bottom of the molding cavity, the copper being heated up to 300-600° C., and molten aluminum being filled into the molding cavity using a gravity casing process to create diffusion bonding to the interface between the copper and aluminum materials, molten aluminum being cooled and cured to avail an integrated compound laminate in a given profile of heterogeneous copper and aluminum.Type: GrantFiled: October 1, 2003Date of Patent: August 30, 2005Assignee: Loyalty Founder Enterprise Co., Ltd.Inventors: Yung-chen Chen, Chuan-Cheng Huang, Jia-Jen Yeh
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Publication number: 20050072546Abstract: A sink compound laminate modeling process having a copper material in thickness of 0.1˜0.8 mm placed at the bottom of the modeling cavity with the bottom of the copper laminate fully bound to the bottom of the modeling cavity, the copper being heated up to 300˜650° C., and melting aluminum being filled into the modeling cavity using gravity casing process to create diffused lamination to the interface between the copper and aluminum materials, melting aluminum being cooled and cured to avail an integrated compound laminate in a given profile of heterogeneous copper and aluminum.Type: ApplicationFiled: October 1, 2003Publication date: April 7, 2005Inventors: Yung-Chen Chen, Chuan-Cheng Huang, Jia-Jen Yeh