Patents by Inventor Yung-Chen CHIEN

Yung-Chen CHIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11012057
    Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Chi Huang, Jerry Chang Jui Kao, Chi-Lin Liu, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma, Yung-Chen Chien
  • Publication number: 20210099161
    Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.
    Type: Application
    Filed: September 21, 2020
    Publication date: April 1, 2021
    Inventors: Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien
  • Publication number: 20200350916
    Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Patent number: 10735001
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
  • Publication number: 20200151297
    Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.
    Type: Application
    Filed: July 25, 2019
    Publication date: May 14, 2020
    Inventors: JERRY CHANG JUI KAO, HUI-ZHONG ZHUANG, YUNG-CHEN CHIEN, TING-WEI CHIANG, CHIH-WEI CHANG, XIANGDONG CHEN
  • Publication number: 20190319624
    Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 17, 2019
    Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
  • Publication number: 20190305761
    Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.
    Type: Application
    Filed: March 6, 2019
    Publication date: October 3, 2019
    Inventors: Kai-Chi HUANG, Jerry Chang Jui KAO, Chi-Lin LIU, Lee-Chung LU, Shang-Chih HSIEH, Wei-Hsiang MA, Yung-Chen CHIEN
  • Patent number: 10127976
    Abstract: A static random access memory cell includes a controlling signal line unit, a latch and an access transistor unit. The first bottom transistor unit is controlled by the controlling signal line unit to change voltage levels of the first pseudo node and the second pseudo node. The second bottom transistor unit is controlled by the first internal node to perform connection and disconnection between the controlling signal line unit and the second pseudo node, and the second bottom transistor unit is controlled by the second internal node to perform connection and disconnection between the controlling signal line unit and the first pseudo node. The access transistor unit is controlled by the controlling signal line unit to perform connection and disconnection between the controlling signal line unit, the first pseudo node and the second pseudo node.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 13, 2018
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Jinn-Shyan Wang, Yung-Chen Chien
  • Publication number: 20180261277
    Abstract: A static random access memory cell includes a controlling signal line unit, a latch and an access transistor unit. The first bottom transistor unit is controlled by the controlling signal line unit to change voltage levels of the first pseudo node and the second pseudo node. The second bottom transistor unit is controlled by the first internal node to perform connection and disconnection between the controlling signal line unit and the second pseudo node, and the second bottom transistor unit is controlled by the second internal node to perform connection and disconnection between the controlling signal line unit and the first pseudo node. The access transistor unit is controlled by the controlling signal line unit to perform connection and disconnection between the controlling signal line unit, the first pseudo node and the second pseudo node.
    Type: Application
    Filed: July 21, 2017
    Publication date: September 13, 2018
    Inventors: Jinn-Shyan WANG, Yung-Chen CHIEN