Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

Abstract: The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a resistor region, forming a first gate structure on the resistor region, forming a first interlayer dielectric (ILD) layer around the first gate structure, transforming the first gate structure into a first metal gate having a gate electrode on the substrate and a hard mask on the gate electrode, and then forming a resistor on the first metal gate.

Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

Abstract: A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.