Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and the protection circuit. The protection circuit including a first protection transistor pair and a second protection transistor pair is set between the latch circuit and the input circuit, and is configured to prevent an excessive voltage drop between the input circuit and a pair of output terminals, wherein the pair of output terminals is set between the first and the second protection transistor pairs and used for outputting a pair of output signals. The input circuit includes an input transistor pair coupled between the second protection transistor pair and a low-voltage terminal and configured to operate according to a pair of input signals.

Abstract: A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.

Abstract: A master electronic device used to perform communication with a slave electronic device is provided. The master electronic device includes a power module, an input and output (I/O) module, a processing module, a sample and hold module and a control module. The power module outputs power having a default operation voltage. The I/O module operates according to the power having the default operation voltage. The processing module controls the I/O module to generate and transmit a command signal to the slave electronic device. The sample and hold module receives and samples a response signal from the slave electronic device. The control module determines a slave operation voltage according to a high state voltage level of the response signal, so as to further control the power module to generate power having the slave operation voltage such that the I/O module operates accordingly.

Abstract: A master electronic device used to perform communication with a slave electronic device is provided. The master electronic device includes a power module, an input and output (I/O) module, a processing module, a sample and hold module and a control module. The power module outputs power having a default operation voltage. The I/O module operates according to the power having the default operation voltage. The processing module controls the I/O module to generate and transmit a command signal to the slave electronic device. The sample and hold module receives and samples a response signal from the slave electronic device. The control module determines a slave operation voltage according to a high state voltage level of the response signal, so as to further control the power module to generate power having the slave operation voltage such that the I/O module operates accordingly.