Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.

Abstract: Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.

Abstract: Embodiments discloses herein describe methods for treating a substrate. In one example, a method of treating a layer of a film stack includes pre-treating a surface of an underlayer of a film stack formed on a substrate and forming a metal oxide in a photoresist layer of the film stack by heating a methyl-containing material in a processing environment proximate a film stack. The film stack includes the photoresist layer disposed on top of and in contact with an underlayer, and the underlayer disposed on top of a substrate. The metal oxide implanted photoresist later is then etched.

Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.

Abstract: Embodiments of the present disclosure generally relate to methods for etching materials. In one or more embodiments, the method includes positioning a substrate in a process volume of a process chamber, where the substrate includes a metallic ruthenium layer disposed thereon, and exposing the metallic ruthenium layer to an oxygen plasma to produce a solid ruthenium oxide on the metallic ruthenium layer and a gaseous ruthenium oxide within the process volume. The method also includes exposing the solid ruthenium oxide to a secondary plasma to convert the solid ruthenium oxide to either metallic ruthenium or a ruthenium oxychloride compound. The metallic ruthenium is in a solid state on the metallic ruthenium layer or the ruthenium oxychloride compound is in a gaseous state within the process volume.

Abstract: Embodiments disclosed herein include a method of developing a patterning stack. In an embodiment, the method comprises providing a patterning stack, where the patterning stack comprises an underlayer and a photoresist over the underlayer, and where the underlayer has a first adhesion strength with the photoresist. The method may further comprise exposing and developing the photoresist with electromagnetic radiation and a developer, where scum remains on a surface of the underlayer. In an embodiment, the method further comprises treating the underlayer so that the underlayer has a second adhesion strength with the scum, and removing the scum.

Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.

Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.

Abstract: Embodiments of the present disclosure generally relate to methods for enhancing carbon hardmask to have improved etching selectivity and profile control. In some embodiments, a method of treating a carbon hardmask layer is provided and includes positioning a workpiece within a process region of a processing chamber, where the workpiece has a carbon hardmask layer disposed on or over an underlying layer, and treating the carbon hardmask layer by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce an aluminum oxide carbon hybrid hardmask which is denser than the carbon hardmask layer. The SIS process includes exposing and infiltrating the carbon hardmask layer with an aluminum precursor, purging to remove gaseous remnants, exposing and infiltrating the carbon hardmask layer to an oxidizing agent to produce an aluminum oxide coating disposed on inner surfaces of the carbon hardmask layer, and purging the process region to remove gaseous remnants.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

Abstract: A method of forming features over a semiconductor substrate is provided. The method includes supplying a gas mixture over a surface of a substrate at a continuous flow rate. A first radio frequency (RF) signal is delivered to an electrode while the gas mixture is supplied at the continuous flow rate to deposit a polymer layer over the surface of the substrate. The surface of the substrate includes an oxide containing portion and a nitride containing portion. A second RF signal is delivered to the electrode while continuously supplying the gas mixture at the continuous flow rate to selectively etch the oxide containing portion relative to the nitride containing portion.

Abstract: Embodiments of the present disclosure generally relate to methods for enhancing photoresist (PR) to have improved profile control. A method for treating a PR includes positioning a workpiece within a process region of a processing chamber, where the workpiece contains a patterned PR disposed on an underlayer, and treating the patterned PR by exposing the workpiece to a sequential infiltration synthesis (SIS) process to produce a treated patterned PR which is denser and harder than the patterned PR. The SIS process includes one or more infiltration cycles of exposing the patterned PR to a precursor containing silicon or boron, infiltrating the patterned PR with the precursor, purging to remove remnants of the precursor, exposing the patterned PR to an oxidizing agent, infiltrating the patterned PR with the oxidizing agent to produce oxide coating disposed on inner surfaces of the patterned PR, and purging to remove remnants of the oxidizing agent.

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

Abstract: Methods for formation of a layer stack during a back-end-of-line (BEOL) process flow and the layer stack formed therefrom are provided. In one or more embodiments, the method utilizes a two-dimensional (2D) self-aligned scheme with a subtractive metal etch. The method includes using a hard mask to form a via with a small width which is formed through or contacts each of a first metal layer and a second metal layer. The via is filled with a metal gapfill to connect the first metal layer and the second metal layer. Each of the first metal layer and the second metal layer are patterned to form a plurality of features.

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

Abstract: Embodiments of the present disclosure generally relate to methods for etching materials. In one or more embodiments, the method includes positioning a substrate in a process volume of a process chamber, where the substrate includes a metallic ruthenium layer disposed thereon, and exposing the metallic ruthenium layer to an oxygen plasma to produce a solid ruthenium oxide on the metallic ruthenium layer and a gaseous ruthenium oxide within the process volume. The method also includes exposing the solid ruthenium oxide to a secondary plasma to convert the solid ruthenium oxide to either metallic ruthenium or a ruthenium oxychloride compound. The metallic ruthenium is in a solid state on the metallic ruthenium layer or the ruthenium oxychloride compound is in a gaseous state within the process volume.

Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.

Abstract: The disclosure provides an eye tracking method, an head-mounted display (HMD), and a computer readable storage medium. The method includes: capturing, by the first camera, a first eye image of a first eye of a wearer of the HMD; capturing, by the second camera, a second eye image of the first eye of the wearer; constructing a first eye model of the first eye based on the first eye image and the second eye image; capturing, by the first camera, a first specific eye image of the first eye of the wearer; obtaining a plurality of first specific eye landmarks in the first specific eye image; identifying a first eye pose of the first eye of the wearer based on the first eye model and the first specific eye landmarks.

Abstract: Methods for depositing boron-containing films on a substrate are described. The substrate is exposed to a boron precursor and a plasma to form the boron-containing film (e.g., elemental boron, boron oxide, boron carbide, boron silicide, boron nitride). The exposures can be sequential or simultaneous. The boron-containing films are selectively deposited on one material (e.g., SiN or Si) rather than on another material (e.g., silicon oxide).

Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.