Patents by Inventor Yung-Cheng Lin

Yung-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 11900586
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20230290715
    Abstract: A ball grid array (BGA) package for use in a touch panel controller includes a package substrate and a plurality of solder bumps. The plurality of solder bumps are disposed on the package substrate, arranged in a staggered pattern surrounding a hollow region on the package substrate, and coupled to electrodes of a touch panel via a multi-layer circuit board. The staggered pattern includes Ys1 top rows and Ys2 bottom rows, a minimum vertical distance between centers of two vertically adjacent solder bumps in the Ys1 top rows and the Ys2 bottom rows being referred to as an equivalent vertical pitch, and Ys1, Ys2 being integers exceeding 2. the hollow region has a minimum length defined by the minimum length=((Ys1?2)+(Ys2?2))*the equivalent vertical pitch.
    Type: Application
    Filed: November 20, 2022
    Publication date: September 14, 2023
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Tsung-Ling Li, Yung-Cheng Lin, Ju-Lin Huang
  • Patent number: 11196425
    Abstract: An eye width monitor (EWM) for a clock and data recovery (CDR) circuit includes a delay circuit, a first multiplexer (MUX) and a calibration circuit. The delay circuit includes an input terminal and an output terminal. The first MUX, coupled to the delay circuit, includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first MUX is coupled to a clock input terminal of the EWM. The second input terminal of the first MUX is coupled to the output terminal of the delay circuit. The output terminal of the first MUX is coupled to the input terminal of the delay circuit. The calibration circuit, coupled to the delay circuit, is configured to receive an oscillation clock from the delay circuit and receive a reference clock, and calibrate the oscillation clock with the reference clock.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: December 7, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Che-Yi Lin, Yung-Cheng Lin
  • Publication number: 20210118125
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10872406
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10614766
    Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: April 7, 2020
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Ren-Hong Luo, Shih-Chun Lin, Yung-Cheng Lin, Mu-Jung Chen
  • Publication number: 20190318471
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: August 29, 2018
    Publication date: October 17, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20170337886
    Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 23, 2017
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Ren-Hong LUO, Shih-Chun LIN, Yung-Cheng LIN, Mu-Jung CHEN
  • Patent number: 9800265
    Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: October 24, 2017
    Assignee: Novatek Microelectronics Corp.
    Inventors: Shih-Chun Lin, Ren-Hong Luo, Mu-Jung Chen, Yung-Cheng Lin
  • Publication number: 20170279461
    Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
    Type: Application
    Filed: January 18, 2017
    Publication date: September 28, 2017
    Applicant: Novatek Microelectronics Corp.
    Inventors: Shih-Chun Lin, Ren-Hong Luo, Mu-Jung Chen, Yung-Cheng Lin
  • Patent number: 9583816
    Abstract: A wireless transceiver includes at least one antenna, a substrate, and a mechanical part on which the at least one antenna is disposed, wherein a relative position between the at least one antenna and the substrate is changed when an external force is applied to the mechanical part.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: February 28, 2017
    Assignee: Wistron NeWeb Corporation
    Inventors: Yung-Cheng Lin, Chien-Ming Peng
  • Patent number: 9544123
    Abstract: The present invention provides an electronic device including a coupler, a noise-estimation apparatus and an assembly unit. The coupler receives a baseband signal. The noise-estimation apparatus receives the baseband signal and subtracts a predetermined synchronization preamble from the baseband signal to obtain a noise-estimation signal, and the predetermined synchronization preamble is a transmission signal that conforms to the standards of 802.11bg and/or IEEE 802.11n. The assembly unit receives the baseband signal and subtracts a noise-estimation signal from the baseband signal to obtain an output signal.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 10, 2017
    Assignee: WISTRON NEWEB CORP.
    Inventors: Chen-Chao Chang, Yung-Cheng Lin
  • Publication number: 20160223390
    Abstract: A wireless sensing device including a vibration plate, an antenna, a sensor, an energy harvesting circuit and a data processing circuit is provided. The antenna and the sensor are disposed on the vibration plate. The sensor generates a sensing data according to the vibration of the vibration plate. The energy harvesting circuit generates an electrical energy in response to the vibration of the vibration plate. The data processing circuit is coupled to the sensor and the antenna, and the data processing circuit is operated by the electrical energy to store the sensing data, or to transmit the sensing data through the antenna.
    Type: Application
    Filed: September 24, 2015
    Publication date: August 4, 2016
    Inventor: Yung-Cheng Lin
  • Patent number: 9264920
    Abstract: A network managing method is utilized for a wireless network system. The wireless network includes multiple wireless access equipments and multiple user equipments. The method uses the wireless access equipments to measure a plurality of echo back time of the user equipments to obtain multiple measurement results, determines locations of the user equipments according to the measurement results and locations of the wireless access equipments, and adjusts wireless operations from the wireless access equipments to the user equipments according to the locations and priorities of the user equipments.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 16, 2016
    Assignee: Wiston NeWeb Corporation
    Inventor: Yung-Cheng Lin
  • Publication number: 20150364811
    Abstract: A wireless transceiver includes at least one antenna, a substrate, and a mechanical part on which the at least one antenna is disposed, wherein a relative position between the at least one antenna and the substrate is changed when an external force is applied to the mechanical part.
    Type: Application
    Filed: September 22, 2014
    Publication date: December 17, 2015
    Inventors: Yung-Cheng Lin, Chien-Ming Peng
  • Publication number: 20150280773
    Abstract: An antenna distribution controller including a plurality of antenna connectors, at least one device connector, an antenna switching circuit and a controller is provided. The antenna connector is configured to connect an external antenna. The device connector is configured to connect an external wireless communication device. The antenna switching circuit has a plurality of antenna ports and at least one device port. These antenna ports are coupled to one of the antenna connectors, respectively. The device port is coupled to the device connector. The controller is coupled to a control terminal of the antenna switching circuit for controlling an electrical connection relationship between the antenna ports and the device port.
    Type: Application
    Filed: May 19, 2014
    Publication date: October 1, 2015
    Applicant: Wistron NeWeb Corp.
    Inventors: Chen-Chao Chang, Yung-Cheng Lin
  • Publication number: 20150078199
    Abstract: A network managing method for a wireless network system including a plurality of wireless access equipments and at least one user equipment includes the plurality of wireless access equipments measuring a plurality of echo back time of the at least one user equipment to obtain a plurality of measurement results, determining locations of the at least one user equipment according to the plurality of measurement results and locations of the plurality of wireless access equipments, and adjusting wireless operations from the plurality of wireless access equipments to the at least one user equipment according to the locations and priorities of the at least one user equipment.
    Type: Application
    Filed: February 25, 2014
    Publication date: March 19, 2015
    Applicant: Wistron NeWeb Corporation
    Inventor: Yung-Cheng Lin
  • Publication number: 20140269607
    Abstract: The present invention provides an electronic device including a coupler, a noise-estimation apparatus and an assembly unit. The coupler receives a baseband signal. The noise-estimation apparatus receives the baseband signal and subtracts a predetermined synchronization preamble from the baseband signal to obtain a noise-estimation signal, and the predetermined synchronization preamble is a transmission signal that conforms to the standards of 802.11bg and/or IEEE 802.11n. The assembly unit receives the baseband signal and subtracts a noise-estimation signal from the baseband signal to obtain an output signal.
    Type: Application
    Filed: August 14, 2013
    Publication date: September 18, 2014
    Applicant: Wistron NeWeb Corp.
    Inventors: Chen-Chao CHANG, Yung-Cheng LIN
  • Patent number: 8743753
    Abstract: A digital signage system, includes: a gateway device, coupled to a network; at least one first hot spot, including: an adaptor box, coupled to the gateway device, downloading a content transmitted through the network via the gateway device; a first access point device, coupled to the gateway device, downloading a service on the network via the gateway device; and a display device, coupled to the adaptor box, displaying the content through the adaptor box, and at least one second hot spot, including: a second access point device, coupled to the gateway device, downloading the service via the gateway device, wherein the first access point device and the second access point device provide the service to at least one mobile terminal through wireless communication.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: June 3, 2014
    Assignee: Wistron NeWeb Corp.
    Inventors: Yung-Cheng Lin, Kuo-Feng Huang