Abstract: A method and device of removing and recycling metals from a mixing acid solution, includes adsorbing a mixing acid solution with a pH value of ?1 to 4 and a cobalt ion concentration of 100 to 1,000 mg/L by at least two cation resins in series setting to the cobalt ion concentration in the mixing acid solution is less than 10 mg/L, and then adjusting the pH value of the mixing acid solution after adsorption to meet a discharge standard, wherein the particle size of the at least two cation resins in series setting is 150˜1,200 ?m. After the cation resins are saturated by adsorption, regenerating the cation resins by sulfuric acid to form a cobalt sulfate solution, and then electrolytically treating the cobalt sulfate solution to obtain electrolytic cobalt and sulfuric acid electrolyte. The operation process is simple without complicated equipment, and it can effectively recycle metals from mixing acid solutions.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first III-V compound layer disposed on the substrate, a second III-V compound layer disposed on the first III-V compound layer, a p-type doped III-V compound layer disposed on the second III-V compound layer, a gate disposed over the p-type doped III-V compound layer, a source and a drain disposed on opposite sides of the gate, and a dielectric layer disposed between the p-type doped III-V compound layer and the gate. A method for forming the above semiconductor device is also provided.

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Abstract: A method for treating wastewater containing ertriazole compounds is provided. Hypochlorous acid (HOCl) having a neutral to slightly acidic pH value is added to the wastewater containing triazole compounds for reaction, thereby effectively reacting more than 90% of triazole compounds.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A ball grid array (BGA) package for use in a touch panel controller includes a package substrate and a plurality of solder bumps. The plurality of solder bumps are disposed on the package substrate, arranged in a staggered pattern surrounding a hollow region on the package substrate, and coupled to electrodes of a touch panel via a multi-layer circuit board. The staggered pattern includes Ys1 top rows and Ys2 bottom rows, a minimum vertical distance between centers of two vertically adjacent solder bumps in the Ys1 top rows and the Ys2 bottom rows being referred to as an equivalent vertical pitch, and Ys1, Ys2 being integers exceeding 2. the hollow region has a minimum length defined by the minimum length=((Ys1?2)+(Ys2?2))*the equivalent vertical pitch.

Abstract: An eye width monitor (EWM) for a clock and data recovery (CDR) circuit includes a delay circuit, a first multiplexer (MUX) and a calibration circuit. The delay circuit includes an input terminal and an output terminal. The first MUX, coupled to the delay circuit, includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first MUX is coupled to a clock input terminal of the EWM. The second input terminal of the first MUX is coupled to the output terminal of the delay circuit. The output terminal of the first MUX is coupled to the input terminal of the delay circuit. The calibration circuit, coupled to the delay circuit, is configured to receive an oscillation clock from the delay circuit and receive a reference clock, and calibrate the oscillation clock with the reference clock.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.

Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.

Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

Abstract: A wireless transceiver includes at least one antenna, a substrate, and a mechanical part on which the at least one antenna is disposed, wherein a relative position between the at least one antenna and the substrate is changed when an external force is applied to the mechanical part.