Patents by Inventor Yung-Cheng Lu
Yung-Cheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250253246Abstract: A semiconductor device includes a substrate. A gate structure is over the substrate. Source/drain epitaxial structures are on opposite sides of the gate structure. An interlayer dielectric (ILD) structure surrounds and covers the gate structure. A dielectric liner lines a sidewall of the ILD structure and wraps a top corner of the gate structure. The dielectric liner comprises a bottom portion, a top portion above the bottom portion, and a middle portion connecting the bottom portion and the top portion, wherein the middle portion has a different composition than the bottom portion and the top portion.Type: ApplicationFiled: February 6, 2024Publication date: August 7, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han YEH, Yu-Lien HUANG, Yuan-Sheng HUANG, Yung-Cheng LU
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Patent number: 12363979Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.Type: GrantFiled: May 10, 2024Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kai Lin, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui
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Patent number: 12336211Abstract: A method of forming a semiconductor device includes forming a first layer on a semiconductor fin; forming a mask on the first layer, the mask being thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The first layer is thinned along the sidewall of the semiconductor fin using the mask. A second layer is formed on the semiconductor fin, the second layer covering the mask and the first layer. A dummy gate layer is formed on the semiconductor fin and patterned to expose a top surface of the semiconductor fin.Type: GrantFiled: August 4, 2021Date of Patent: June 17, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-I Lin, Ming-Ho Lin, Chun-Heng Chen, Yung-Cheng Lu
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Semiconductor Device Including Multiple Inner Spacers with Different Etch Rates and Method of Making
Publication number: 20250194202Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.Type: ApplicationFiled: February 7, 2025Publication date: June 12, 2025Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu -
Patent number: 12324208Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.Type: GrantFiled: January 29, 2024Date of Patent: June 3, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
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Publication number: 20250176204Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.Type: ApplicationFiled: January 27, 2025Publication date: May 29, 2025Inventors: Te-En Cheng, Yung-Cheng Lu, Chi On Chui, Wei-Yang Lee
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Patent number: 12288814Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.Type: GrantFiled: January 24, 2024Date of Patent: April 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
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Publication number: 20250126822Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.Type: ApplicationFiled: December 27, 2024Publication date: April 17, 2025Inventors: Wan-Yi Kao, Fang-Yi Liao, Shu Ling Liao, Yen-Chun Huang, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
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Publication number: 20250118569Abstract: A method includes following steps. A target layer is formed over a substrate. A first hard mask layer is formed over the target layer by a plasma generated using a first radio frequency generator and a second radio frequency generator. The first radio frequency generator and the second radio frequency generator have different powers. A second hard mask layer is formed over the first hard mask layer by a plasma generated using the first radio frequency generator without using the second radio frequency generator. A photoresist layer is formed over the second hard mask layer. The photoresist layer is exposed. The photoresist layer is developed. The first hard mask layer and the second hard mask layer are patterned using the photoresist layer as an etch mask. The target layer is patterned using the first hard mask layer and the second hard mask layer as an etch mask.Type: ApplicationFiled: October 5, 2023Publication date: April 10, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Cheng LIU, Wei-Zhong CHEN, Chi-Ming YANG, Jr-Hung LI, Yung-Cheng LU
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Patent number: 12266728Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.Type: GrantFiled: February 29, 2024Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Yi Kao, Yu-Cheng Shiau, Chunyao Wang, Chih-Tang Peng, Yung-Cheng Lu, Chi On Chui
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Patent number: 12255205Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.Type: GrantFiled: May 27, 2022Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chieh-Ping Wang, Tai-Chun Huang, Yung-Cheng Lu, Ting-Gang Chen, Chi On Chui
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Semiconductor device including multiple inner spacers with different etch rates and method of making
Patent number: 12249639Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.Type: GrantFiled: January 2, 2024Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu -
Patent number: 12237399Abstract: A method of forming a semiconductor device includes forming a sacrificial layer over a first stack of nanostructures and an isolation region. A dummy gate structure is formed over the first stack of nanostructures, and a first portion of the sacrificial layer. A second portion of the sacrificial layer is removed to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure. A spacer layer is formed over the dummy gate structure. A first portion of the spacer layer physically contacts the first stack of nanostructures.Type: GrantFiled: August 27, 2021Date of Patent: February 25, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Te-En Cheng, Yung-Cheng Lu, Chi On Chui, Wei-Yang Lee
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Publication number: 20250048726Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.Type: ApplicationFiled: October 25, 2024Publication date: February 6, 2025Inventors: Wan-Yi Kao, Hung Cheng Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui
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Patent number: 12218221Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.Type: GrantFiled: May 13, 2022Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Yi Kao, Fang-Yi Liao, Shu Ling Liao, Yen-Chun Huang, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
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Patent number: 12206012Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.Type: GrantFiled: May 28, 2021Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Szu-Ying Chen
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Patent number: 12206013Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.Type: GrantFiled: June 30, 2023Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Yi Kao, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui, Hung Cheng Lin
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Publication number: 20250006500Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.Type: ApplicationFiled: July 2, 2024Publication date: January 2, 2025Inventors: Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui, Yung-Cheng Lu
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Patent number: 12176349Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.Type: GrantFiled: June 15, 2023Date of Patent: December 24, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Yi Kao, Hung Cheng Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui
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Publication number: 20240413150Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.Type: ApplicationFiled: July 31, 2024Publication date: December 12, 2024Applicant: Taiwan Semiconductor Manufacturing Company , Ltd.Inventors: Chieh-Ping Wang, Tai-Chun Huang, Yung-Cheng Lu, Ting-Gang Chen, Chi On Chui