Abstract: A method for cleaning valid bits in a cache memory is provided. The method includes performing a valid-bit-cleaning process to sequentially clean a valid bit corresponding to each address of the cache memory when an integrated circuit is booted up or enters a working state from a sleep mode. In response to a flash memory controller reading data from a specific address of the flash memory, the method includes notifying the cache memory controller to suspend the valid-bit-cleaning process, and utilizing the cache memory controller to write the data into the specific address of the cache memory and to set the valid bit corresponding to the specific address as valid. In response to the valid bit being set as valid, the method includes reading the data from the specific address of the cache memory, transmitting the data to the processor, and resuming the valid-bit-cleaning process.

Abstract: A clock filter device for finding an optimal cut-off frequency of a clock filter through a controller to achieve an effective clock filtering is illustrated. Further, in the calibration mode, a reference clock that has not passed the clock filter and a reference clock that has passed the clock filter make a first counter and a second counter count respectively. After the first counter counts to a specific value, a count value of the second counter is obtained. The count values of the first counter and the second counter are compared to each other to determine whether the two values are approximate or not. When the two values are not approximate, the previous cut-off frequency of the clock filter is taken as the optimal cut-off frequency. Therefore, the clock filter can adopt the optimal cut-off frequency in a working mode to effectively filter out the noise an input clock.

Abstract: A power consumption evaluation device and a power consumption evaluation method are provided. The power consumption evaluation device includes a power converter, a counter, and a controller. The power converter includes a power switch. The power switch performs a switching operation according to a control signal, so that the power converter supplies power to a corresponding load among at least one load. The counter counts one of a positive pulse and a negative pulse of the control signal during a measurement period to obtain a count value. The controller generates an evaluation result of the corresponding load according to the count value.

Abstract: A clock filter device for finding an optimal cut-off frequency of a clock filter through a controller to achieve an effective clock filtering is illustrated. Further, in the calibration mode, a reference clock that has not passed the clock filter and a reference clock that has passed the clock filter make a first counter and a second counter count respectively. After the first counter counts to a specific value, a count value of the second counter is obtained. The count values of the first counter and the second counter are compared to each other to determine whether the two values are approximate or not. When the two values are not approximate, the previous cut-off frequency of the clock filter is taken as the optimal cut-off frequency. Therefore, the clock filter can adopt the optimal cut-off frequency in a working mode to effectively filter out the noise an input clock.

Abstract: A clock-gating synchronization circuit is provided. The clock-gating synchronization circuit includes a synchronization circuit and clock-gating circuit. The synchronization circuit is configured to perform a synchronization operation to convert a first control signal in a first clock domain into a second control signal in a second clock domain, transmit the second control signal to an electronic circuit, and determine whether the first control signal and the second control signal are the same to generate a first signal. The clock-gating circuit is configured to perform clock gating on the clock signal from a clock generator in the second clock domain according to the first signal to generate a gated clock signal, and transmit the gated clock signal to the electronic circuit and the synchronization circuit, wherein the synchronization operation performed by the synchronization circuit is controlled by the gated clock signal.

Abstract: An encryption and decryption system includes a first electronic device and a second electronic device. The first electronic device includes a memory device and an encryption device. The memory device can store plaintext data. The encryption device can generate first pseudo data and first pseudo key. The encryption device encrypts first pseudo data by the first pseudo key and encrypt the plaintext data by a key, and outputs the ciphertext data generated by encrypting plaintext data by the key. The second electronic device includes a decryption device for generating second pseudo data and the second pseudo key. The decryption device decrypts the second pseudo data by the second pseudo key, and decrypts the ciphertext data by the key, and outputs the plaintext data, which is generated by decrypting the ciphertext data by the key.

Abstract: A clock-gating synchronization circuit is provided. The clock-gating synchronization circuit includes a synchronization circuit and clock-gating circuit. The synchronization circuit is configured to perform a synchronization operation to convert a first control signal in a first clock domain into a second control signal in a second clock domain, transmit the second control signal to an electronic circuit, and determine whether the first control signal and the second control signal are the same to generate a first signal. The clock-gating circuit is configured to perform clock gating on the clock signal from a clock generator in the second clock domain according to the first signal to generate a gated clock signal, and transmit the gated. clock signal to the electronic circuit and the synchronization circuit, wherein the synchronization operation performed by the synchronization circuit is controlled by the gated clock signal.

Abstract: A control device for adjusting the output voltage of a voltage generator, wherein the control device includes a master circuit, a slave circuit, and a power-scaling control circuit, is provided. The master circuit is coupled to a system bus. The slave circuit is coupled to the system bus. The power-scaling control circuit is coupled between the master circuit and the slave circuit. In response to the master circuit sending a voltage-scaling command, the power-scaling control circuit sets a control signal at a suspension level so that the slave circuit sets a specific signal transmitted by the system bus at a wait level. In response to the specific signal being at the wait level, the master circuit stops accessing the first specific device of the slave circuit. In response to the control signal being at the suspension level, the power-scaling control circuit adjusts the output voltage.

Abstract: A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

Abstract: A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

Abstract: A control device for adjusting the output voltage of a voltage generator, wherein the control device includes a master circuit, a slave circuit, and a power-scaling control circuit, is provided. The master circuit is coupled to a system bus. The slave circuit is coupled to the system bus. The power-scaling control circuit is coupled between the master circuit and the slave circuit. In response to the master circuit sending a voltage-scaling command, the power-scaling control circuit sets a control signal at a suspension level so that the slave circuit sets a specific signal transmitted by the system bus at a wait level. In response to the specific signal being at the wait level, the master circuit stops accessing the first specific device of the slave circuit. In response to the control signal being at the suspension level, the power-scaling control circuit adjusts the output voltage.

Abstract: A clock glitch detection circuit includes a detection circuit and a logic circuit. The detection circuit is configured to receive a clock input signal and a clock output signal and determines whether the clock input signal and the clock output signal are in phase, so as to output a first detection signal and a second detection signal. The logic circuit is coupled to the detection circuit and configured to receive the first detection signal and the second detection signal. The logic circuit determines whether the first detection signal and the second detection signal are in phase, so as to generate a glitch detection signal. The glitch detection signal is configured to indicate whether clock glitch occurs in the clock input signal.

Abstract: An encryption and decryption system includes a first electronic device and a second electronic device. The first electronic device includes a memory device and an encryption device. The memory device can store plaintext data. The encryption device can generate first pseudo data and first pseudo key. The encryption device encrypts first pseudo data by the first pseudo key and encrypt the plaintext data by a key, and outputs the ciphertext data generated by encrypting plaintext data by the key. The second electronic device includes a decryption device for generating second pseudo data and the second pseudo key. The decryption device decrypts the second pseudo data by the second pseudo key, and decrypts the ciphertext data by the key, and outputs the plaintext data, which is generated by decrypting the ciphertext data by the key.