Patents by Inventor Yung-Chi Lee

Yung-Chi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136463
    Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 25, 2024
    Applicant: EPISTAR CORPORATION
    Inventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
  • Publication number: 20240102194
    Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.
    Type: Application
    Filed: August 7, 2023
    Publication date: March 28, 2024
    Inventors: Cheng-EN HO, Yu-Lian CHEN, Cheng-Chi WANG, Yu-Jen CHANG, Yung-Sheng LU, Cheng-Yu LEE, Yu-Ming LIN
  • Publication number: 20240080505
    Abstract: A method, comprising: detecting an outage of at least one functionality in a live streaming; performing an first operation toward a second user terminal; storing data of the first operation in a database of the first user terminal; and displaying an effect corresponding to the first operation during the outage. The present disclosure may store the data of operation performed by the user terminal during outage and process the operation after the outage is recovered. Therefore, the streamers and viewers may feel interested and satisfied, instead of feeling anxious, and the user experience may be enhanced.
    Type: Application
    Filed: June 23, 2023
    Publication date: March 7, 2024
    Inventors: Yung-Chi HSU, Hsing-Yu TSAI, Chia-Han CHANG, Yi-Jou LEE, Ming-Che CHENG
  • Publication number: 20180250232
    Abstract: A process for preparing spray dried solid dispersions of (S)—N-(3-(6-isopropoxypyridin-3-yl)-1H4ndazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-dihydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide amorphous free base and hypromellose acetate succinate for pharmaceutical preparations including pharmaceutical capsule preparations.
    Type: Application
    Filed: August 29, 2016
    Publication date: September 6, 2018
    Applicant: Merck Sharp & Dohme Corp.
    Inventors: Yung-Chi Lee, Dan Zhang
  • Patent number: 10058544
    Abstract: The invention includes a granular composition comprising the active ingredient (S)—N-(3-(6-isopropoxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-dihydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide, wherein a total amount of active ingredient comprises by weight % about 60-90% (S)—N-(3-(6-isopro-poxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-di-hydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide Form 1 HCl, about 10-30% (S)—N-(3-(6-isopropoxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-dihydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide amorphous HCl, and about 0-5% (S)—N-(3-(6-isopropoxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-dihydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide amorphous free base.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 28, 2018
    Assignee: Merck Sharp & Dohme Corp.
    Inventors: Deepak Bahl, Yung-Chi Lee, Alfred Lee, William Anthony Marinaro, Jr., Dan Zhang, Tao Feng
  • Publication number: 20180228826
    Abstract: The present disclosure is directed to compositions comprising blended materials comprising a substantially crystalline HCV nucleotide polymerase inhibitor; a first solid dispersion formulation, which comprises an HCV NS5a inhibitor or a pharmaceutically acceptable salt thereof, one or more pharmaceutically acceptable polymers or a mixture thereof; and optionally one or more pharmaceutically acceptable surfactants or a mixture thereof; and optionally one or more excipients; and a second solid dispersion formulation, which comprises an HCV NS3 inhibitor or a pharmaceutically acceptable salt thereof, one or more pharmaceutically acceptable polymers or a mixture thereof; and optionally one or more pharmaceutically acceptable surfactants or a mixture thereof; and optionally one or more excipients.
    Type: Application
    Filed: July 29, 2016
    Publication date: August 16, 2018
    Applicant: MERCK SHARP & DOHME CORP.
    Inventors: David Harris, James DiNunzio, William A Marinaro, Sutthilug Sotthivirat, Chad David Brown, Sundeep Sudish Dhareshwar, Jesse Lee Kuiper, Yung-Chi Lee, Craig Alfred McKelvey, Michael McNevin, Elise Topol Miller, Li Xiong
  • Publication number: 20180228827
    Abstract: The present disclosure is directed to compositions comprising blended materials comprising a substantially crystalline HCV nucleotide polymerase inhibitor; a solid dispersion formulation, which comprises an HCV NS5a inhibitor or a pharmaceutically acceptable salt thereof, one or more pharmaceutically acceptable polymers or a mixture thereof, and optionally one or more pharmaceutically acceptable surfactants or a mixture thereof; and optionally one or more pharmaceutically acceptable surfactants or a mixture thereof; and optionally one or more excipients.
    Type: Application
    Filed: July 29, 2016
    Publication date: August 16, 2018
    Applicant: MERCK SHARP & DOHME CORP.
    Inventors: William A Marinaro, David Harris, James DiNunzio, Sutthilug Sotthivirat, Sundeep Sudish Dhareshwar, Gerard Ross Klinzing, Jesse Lee Kuiper, Yung-Chi Lee, Craig Alfred McKelvey, Michael McNevin, Li Xiong
  • Publication number: 20180221282
    Abstract: A process for drying a spray dried dispersion, comprising: a) providing a spray-dried dispersion comprising particles wherein the particles comprise an active agent and a polymer and optionally one or more surfactants, the dispersion having an average particle diameter of less than about 100 m; b) blending an amount of silicon dioxide with the dispersion to form a dispersion-silicon dioxide blend, wherein the amount of silicon dioxide relative to the amount of dispersion is between about 0.5 and 2.0% by weight; c) drying the blend with a secondary dryer.
    Type: Application
    Filed: July 29, 2016
    Publication date: August 9, 2018
    Applicant: Merck Sharp & Dohme Corp.
    Inventors: Yung-Chi Lee, David Harris, Justin David Moser, Michael McNevin, Amber Broadbent, Robert Hall, Ari Ericson
  • Publication number: 20180000803
    Abstract: The invention includes a granular composition comprising the active ingredient (S)-N-(3-(6-isopropoxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-dihydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3- carboxamide, wherein a total amount of active ingredient comprises by weight % about 60-90% (5)-N-(3-(6-isopro-poxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-di-hydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide Form 1 HCl, about 10-30% (5)-N-(3-(6-isopropoxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-dihydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide amorphous HCl, and about 0-5% (S)-N-(3-(6-isopropoxypyridin-3-yl)-1H-indazol-5-yl)-1-(2-(4-(4-(1-methyl-1H-1,2,4-triazol-3-yl)phenyl)-3,6-dihydropyridin-1(2H)-yl)-2-oxoethyl)-3-(methylthio)pyrrolidine-3-carboxamide amorphous free base.
    Type: Application
    Filed: December 14, 2015
    Publication date: January 4, 2018
    Applicant: Merck Sharp & Dohme Corp.
    Inventors: Deepak Bahl, Yung-Chi Lee, Alfred Lee, William Anthony Marinaro, Jr., Dan Zhang, Tao Feng
  • Patent number: 7064428
    Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: June 20, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6989326
    Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-bump metallic layer is formed over the active surface of the wafer. A second under-bump metallic layer is formed over the first under-bump metallic layer. A portion of the second under-bump metallic layer is removed to expose the first under-bump metallic layer. A plurality of solder bumps is implanted onto the second under-bump metallic layer. The exposed first under-bump metallic layer is removed so that only the first under-bump metallic layer underneath the second under-bump metallic layer remains.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: January 24, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee
  • Patent number: 6967153
    Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: November 22, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6927964
    Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: August 9, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Publication number: 20050161812
    Abstract: A wafer-level package structure, applicable to a flip-chip type arrangement on a carrier having a plurality of contact points is described. This wafer-level package structure comprises a chip having a protective layer and a plurality of bonding pads and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The wafer-level package structure can further include a heat sink to enhance the heat dissipation ability of the package structure.
    Type: Application
    Filed: April 14, 2005
    Publication date: July 28, 2005
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shou Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6877653
    Abstract: A method of modifying the tin to lead ratio of a tin-lead bump forms a patterned solder mask over a substrate that comprises a first tin-lead bump formed thereon, the patterned solder mask having an opening that exposes the tin-lead bump. A solder material including tin and lead is filled in the opening of the solder mask over the first tin-lead bump. The solder material has a tin to lead ratio that differs from that of the first tin-lead bump. The solder material is reflowed to fuse with the first tin-lead bump, which forms a second tin-lead bump. The tin to lead ratio of the second tin-lead bump is thereby different from that of the first tin-lead bump.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: April 12, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6875683
    Abstract: A method of forming a bump on an active surface of a wafer is disclosed. The method of the invention forms an under ball metallurgy (UBM) onto the active surface of the wafer. Then, the UBM is partially removed until a portion of the active surface of the wafer is exposed. At least one conductive stud is bonded onto the non-removed UBM by wire bonding.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: April 5, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee
  • Patent number: 6861346
    Abstract: A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: March 1, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou
  • Patent number: 6846719
    Abstract: A wafer bump fabrication process is provided in the present invention. A wafer with multiple bonding pads and a passivation layer, which exposes the bonding pads, is provided. The surface of each bonding pad has an under bump metallurgy layer. A patterned photoresist layer with a plurality of opening is formed which openings expose the under bump metallurgy layer. Afterwards a curing process is performed to cure the patterned photoresist layer. Following a solder paste fill-in process is performed to fill a solder paste into the openings. A reflow process is performed to form bumps from the solder paste in the openings. The patterned photoresist layer is removed.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: January 25, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee, Yu-Chen Chou, Tsung-Hua Wu, Su Tao
  • Patent number: 6827252
    Abstract: A method of forming bumps on the active surface of a silicon wafer. An under-ball metallic layer is formed over the active surface of the wafer. A plurality of first solder blocks is attached to the upper surface of the under-ball metallic layer. Each first solder block has an upper surface and a lower surface. The lower surface of each first solder block bonds with the under-ball metallic layer. The upper surfaces of the first solder blocks are planarized. A second solder block is attached to the upper surface of each first solder block and then a reflow operation is carried out.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: December 7, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ho-Ming Tong, Chun-Chi Lee, Jen-Kuang Fang, Min-Lung Huang, Jau-Shoung Chen, Ching-Huei Su, Chao-Fu Weng, Yung-Chi Lee
  • Patent number: 6828664
    Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. The packaging substrate is disposed in a recess of a mold and comprises an outer wall electrically connecting an inner wall of the recess. A first copper-mesh layer and a second copper-mesh layer extend to the outer wall to electrically connect the inner wall of the recess. Static electric charges generated during the molding process are conducted via the first copper-mesh layer or the second copper-mesh layer to the inner wall of the recess and then conducted away. Therefore, the static electric charges generated during the molding process can be safely conducted away from the packaging substrate, preventing the dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: December 7, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Pin Hung, Yung-Chi Lee