Patents by Inventor Yung-Chi Lin

Yung-Chi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12374651
    Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.
    Type: Grant
    Filed: April 2, 2024
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 12374655
    Abstract: A method includes attaching a wafer to a wafer chuck having a curved surface. The method further includes placing a device die on the wafer, such that a first dielectric layer of the device die is in contact with a second dielectric layer of the wafer, and performing an annealing process to bond the first dielectric layer to the second dielectric layer. The method further includes encapsulating the device die with an encapsulating material, forming redistribution lines overlapping the encapsulating material and the device die, and sawing the encapsulating material to form a plurality of packages.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chih Chiou, Yung-Chi Lin, Yen-Ming Chen
  • Publication number: 20250210540
    Abstract: A method includes bonding a top die over a bottom wafer, depositing a stress relief layer on the top die and a top surface of the bottom wafer, forming a dielectric gap-filling layer on the stress relief layer, performing a planarization process on the dielectric gap-filling layer, and sawing the dielectric gap-filling layer and the bottom wafer to form a plurality of packages. One of the packages includes the top die, a portion of the stress relief layer, and a bottom die in the bottom wafer.
    Type: Application
    Filed: March 19, 2024
    Publication date: June 26, 2025
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh
  • Publication number: 20250191941
    Abstract: A method of bonding semiconductor chips is described. The method includes the following steps. A semiconductor wafer is provided on a chuck table of a bonding apparatus. A bond head of the bonding apparatus is driven for picking up a first semiconductor chip from a support, wherein the first semiconductor chip has a first warpage amount. The bond head is driven for moving the first semiconductor chip to a position located over a first bonding region of the semiconductor wafer. A deforming process is performed using a deforming mechanism to deform the chuck table and the first bonding region of the semiconductor wafer by a first deform amount, wherein the first deform amount corresponds to the first warpage amount. The first semiconductor chip is bonded to the first bonding region of the semiconductor wafer while maintaining the first deform amount. The deforming mechanism is released from deforming the chuck table.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 12, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Yang-Chih Hsueh, Yan-Zuo Tsai, Ming-Tsu Chung, Yung-Chi Lin, Yen-Ming Chen
  • Patent number: 12322680
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, Hsiaoyun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20250158005
    Abstract: A wafer on wafer on wafer and a chip on wafer on wafer structure and methods of forming the same are provided. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding and additional device wafers may subsequently be bonded to the first device wafer. A support wafer is then bonded to the top most device wafer and the first wafer may then be removed. The bonded wafer structure may then be singulated into individual semiconductor device packages. Through the wafer-on-wafer bonding process, the manufacturing cost and cycle time may be reduced.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 15, 2025
    Inventors: Yen-Ming Chen, Yung-Chi Lin
  • Publication number: 20250149497
    Abstract: A bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. The hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh
  • Patent number: 12266612
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Patent number: 12261151
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Publication number: 20250070045
    Abstract: In a package device, wherein integrated circuit devices are bonded to a substrate, stress arising from mechanical strain, CTE mismatch, and the like can be alleviated or eliminated by incorporating stress buffering air gaps into a protective material, such as a gap fill oxide. The air gaps can be formed by tuning and changing deposition parameters during the deposition process and/or by tuning the size and placement of adjacent integrated circuit devices in the package, and/or by forming trenches in the protective material prior to the bonding process.
    Type: Application
    Filed: January 3, 2024
    Publication date: February 27, 2025
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh
  • Publication number: 20250062247
    Abstract: A method includes depositing a dielectric layer on a package component having a first warpage, and performing an implantation process to implant the dielectric layer with a stress modulation dopant. After the implantation process, the package component has a second warpage smaller than the first warpage.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 20, 2025
    Inventors: Yang-Chih Hsueh, Yan-Zuo Tsai, Ming-Tsu Chung, Yung-Chi Lin
  • Publication number: 20250062204
    Abstract: A package includes a first die over and bonded to a first side of a second die, where the second die includes a first substrate, a first interconnect structure over the first substrate, a seal ring disposed within the first interconnect structure, first dummy through substrate vias (TSVs) extending through edge regions of the first substrate of the second die and in physical contact with the seal ring, and functional TSVs extending through a central region of the first substrate of the second die.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 20, 2025
    Inventors: Yan-Zuo Tsai, Ming-Tsu Chung, Yang-Chih Hsueh, Yung-Chi Lin
  • Publication number: 20250062136
    Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.
    Type: Application
    Filed: November 20, 2023
    Publication date: February 20, 2025
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh, Ming-Shih Yeh
  • Publication number: 20250006677
    Abstract: A method includes depositing a first dielectric layer as a first surface layer of a first package component, forming a plurality of metal pads in the first dielectric layer, depositing a second dielectric layer as a second surface layer of a second package component, and bonding the second package component to the first package component. The first dielectric layer is bonded to the second dielectric layer. At a time after the bonding, a metal pad in the plurality of metal pads has a top surface contacting a bottom surface of the second dielectric layer.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai
  • Patent number: 12179044
    Abstract: A positive-pressure protective wear has a protective body and an air supply. The protective body has a clothing and a headgear connected with the clothing. The air supply is connected with the protective body and inputs gas into the protective body to keep the protective body under positive pressure, and this can provide an effect of ventilation.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: December 31, 2024
    Inventors: Yung Chi Lin, Chao-Ting Lin, Tzu-Ying Lin
  • Publication number: 20240387465
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Publication number: 20240387393
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Publication number: 20240379505
    Abstract: A method includes forming feature for a first package component, and the forming the feature includes a planarization process to level a top surface of the feature. A silicon-containing dielectric layer is deposited over and contacting the feature, and as a surface feature of the first package component. A second package component is bonded to the silicon-containing dielectric layer through fusion bonding. The silicon-containing dielectric layer has a same thickness in both steps of the depositing and the fusion bonding.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Inventors: Ming-Tsu Chung, Kuang-Wei Cheng, Yung-Chi Lin
  • Publication number: 20240363359
    Abstract: A method includes forming a patterned treating mask over a first surface dielectric layer of a first package component, wherein portions of the first surface dielectric layer are exposed through the patterned treating mask, performing a selective plasma treatment on the portions of the first surface dielectric layer that are exposed through the patterned treating mask to form treated portions, removing the patterned treating mask, and bonding a second surface dielectric layer in a second package component to the first surface dielectric layer.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 31, 2024
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yen-Ming Chen
  • Publication number: 20240321694
    Abstract: A semiconductor device includes a first die. The first die includes a first dielectric bonding layer thereon and a plurality of first dielectric bonding patterns in the first dielectric bonding layer. A composition of the first dielectric bonding patterns is different from a composition of the first dielectric bonding layer.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Ming-Tsu Chung, Yan-Zuo Tsai