Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.

Abstract: A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.

Abstract: A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.

Abstract: A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.

Abstract: A CMP apparatus therefor is provided. First, a substrate including a semiconductor structure, a liner layer over the semiconductor structure and a metal layer over the liner layer is provided. Next, a metal polishing step is performed to polish the metal layer until a portion of the liner layer is exposed. Next, a buffing step is performed to remove any contaminants from the surface of the metal layer. Thereafter, a liner CMP step is performed to polish the liner layer.

Abstract: An apparatus of chemical mechanical polishing has a polishing machine, a first thickness metrology and a second thickness metrology. The first thickness metrology is connected with the polishing machine, and the second thickness metrology is connected with the polishing machine. Since the thickness of the first material layer and the second material layer after polishing process can be separately measured by the first thickness metrology and the second thickness metrology in-situ, the difference of film thickness between wafers can be reduced.

Abstract: A CMP process and a CMP apparatus therefor are provided. First, a substrate including a semiconductor structure, a liner layer over the semiconductor structure and a metal layer over the liner layer is provided. Next, a metal polishing step is performed to polish the metal layer until a portion of the liner layer is exposed. Next, a buffing step is performed to remove any contaminants from the surface of the metal layer. Thereafter, a liner CMP step is performed to polish the liner layer.

Abstract: A CMP slurry delivery system includes a delivery pipe, a first slurry supply reservoir coupled to the delivery pipe for supplying an abrasive, a second slurry supply reservoir coupled to the delivery pipe for supplying a clean chemical, a third slurry supply reservoir coupled to the delivery pipe for supplying a corrosion inhibitor, and a fourth slurry supply reservoir for supplying an oxidizer.

Abstract: A CMP slurry delivery system includes a delivery pipe, a first slurry supply reservoir coupled to the delivery pipe for supplying an abrasive, a second slurry supply reservoir coupled to the delivery pipe for supplying a clean chemical, a third slurry supply reservoir coupled to the delivery pipe for supplying a corrosion inhibitor, and a fourth slurry supply reservoir for supplying an oxidizer.

Abstract: A semiconductor wafer has a top surface and an edge bevel surface, and a first material layer and a second material layer are respectively formed on the top surface and the edge bevel surface. A surface chemical mechanical polishing (surface CMP) process is performed to polish and remove portions of the first material layer down to a first thickness, and a rim CMP process is performed to completely remove the second material layer on the edge bevel surface down to the edge bevel surface thereafter to achieve a smooth surface of the edge bevel surface. Finally, a chemical cleaning process is performed to clean the edge bevel surface and the top surface, and the semiconductor wafer is dried thereafter.

Abstract: A semiconductor wafer has a top surface and an edge bevel surface, and a first material layer and a second material layer are respectively formed on the top surface and the edge bevel surface. A surface chemical mechanical polishing (surface CMP) process is performed to polish and remove portions of the first material layer down to a first thickness, and a rim CMP process is performed to completely remove the second material layer on the edge bevel surface down to the edge bevel surface thereafter to achieve a smooth surface of the edge bevel surface. Finally, a chemical cleaning process is performed to clean the edge bevel surface and the top surface, and the semiconductor wafer is dried thereafter.

Abstract: A method of forming a barrier layer is described. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer, which is conformal to the opening, is formed on the dielectric layer. A first metallic nitride layer, which is conformal to the opening, is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer, which is conformal to the opening, is formed on the first metallic nitride layer.

Abstract: A method of forming a via is provided comprising a plasma treatment at the spin-on-glass layer after forming the unlanding via. The plasma comprises hydrogen and a second gas. The mist containing in the spin-on-glass layer is damaged and removed away.