Abstract: An antenna structure and an electronic device are provided. The electronic device includes a housing and the antenna structure disposed in the housing. The antenna structure includes a grounding element, a feeding radiation element, a feeding element, a first grounding radiation element, and a switching element. The feeding radiation element includes a first radiating portion, a second radiating portion, and a third radiating portion. The first radiating portion and the second radiating portion jointly surround the first grounding radiation element. The first radiating portion and the first grounding radiation element are separate from each other and coupled with each other. The switching element is electrically connected to the first grounding radiation element.

Abstract: An antenna structure and an electronic device are provided. The electronic device includes a housing and the antenna structure disposed therein. The antenna structure includes a grounding element, a feeding radiation element, a feeding element and a first grounding radiation element. The feeding radiation element includes a first radiating portion, a second radiating portion and a third radiating portion. The first radiating portion and the second radiating portion jointly surround the first grounding radiation element. The first radiating portion is spaced apart from and coupled with the first grounding radiation element to generate a first operating frequency band. The second radiating portion is spaced apart from and coupled with the first grounding radiation element to generate a second operating frequency band. The first operating frequency band is lower than the second operating frequency band.

Abstract: An electronic device having an antenna structure is disclosed. The antenna structure includes a substrate, a first radiating portion, a second radiating portion connected to the first radiating portion, a grounding portion, a shorting portion connected between the second radiating portion and the grounding portion, a third radiating portion, a first grounding extension portion connected between the third radiating portion and the grounding portion, and a first capacitive element coupled between a first section and a second section of the shorting portion. The coupling of the shorting portion, the first grounding extension portion, and the third radiating portion generates a first operating frequency band, and the coupling of the first radiating portion, the shorting portion, the first grounding extension portion, and the third radiating portion generates a second operating frequency band, which is higher than the first operating frequency band, through the matching of the first capacitive element.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a cell array. The cell array includes a plurality of first cells arranged in a first column, a plurality of second cells arranged in a second column abutting the first column and a third cell arranged in the first column. Each first cell has a first cell height and is configured to perform a first function. Each second cell has a second cell height and is configured to perform a second function. The third cell has a third cell height and is configured to perform a third function. Each second cell is coupled to and in contact with a respective first cell. The second cell height is greater than the first cell height, and the number of first cells is equal to the number of second cells. The third cell height is proportional to the first cell height.

Abstract: An antenna module is provided. The antenna module includes a circuit board, a conductive layer, and a spiral coil. The circuit board has a first surface and a second surface opposite to each other. The circuit board further includes a first block and a second block connected to each other. The conductive layer is disposed on the first block. The spiral coil is disposed in the second block of the circuit board. The conductive layer at least partially surrounds the spiral coil.

Abstract: An antenna module is provided. The antenna module includes a circuit board, a conductive layer, and a spiral coil. The circuit board has a first surface and a second surface opposite to each other. The circuit board further includes a first block and a second block connected to each other. The conductive layer is disposed on the first block. The spiral coil is disposed in the second block of the circuit board. The conductive layer at least partially surrounds the spiral coil.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: A system and method of testing charging current of a mobile electronic device sets a charging voltage value and a battery voltage value, and sends a control command to a power supply device to generate the charging voltage and the battery voltage. The system and method further receives a charging current value from a current test device under the charging voltage and the battery voltage. Furthermore, the system and method determine if the charging current value falls in an allowable current range and displays test result on a display device.

Abstract: The invention provides a flip-flop. In one embodiment, the flip-flop receives a low swing clock signal, and comprises a first NMOS transistor, a first latch circuit, a second NMOS transistor, and a second latch circuit. The low swing clock signal is inverted to obtain an inverted low swing clock signal. The first NMOS transistor is coupled between a receiving node and a first node, and has a gate coupled to the inverted low swing clock signal. The first latch circuit is coupled between the first node and a second node. The second NMOS transistor is coupled between the second node and a third node. The second latch circuit is coupled between the third node and a fourth node, and generates an output signal on the fourth node.

Abstract: A system and method of testing charging current of a mobile electronic device sets a charging voltage value and a battery voltage value, and sends a control command to a power supply device to generate the charging voltage and the battery voltage. The system and method further receives a charging current value from a current test device under the charging voltage and the battery voltage. Furthermore, the system and method determine if the charging current value falls in an allowable current range and displays test result on a display device.

Abstract: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

Abstract: An integrated circuit has an identification circuit for providing a read-only logic value for identifying the integrated circuit. The identification circuit includes a plurality of programmable stages for determining the read-only logic value. Each of the programmable stages includes a logic cell and a conductive path. The logic cell has an input node connected to an input terminal of the programmable stage, an inverting output node, and a non-inverting output node. The logic value at the non-inverting output node is the same as the logic value at the input node, and the logic value at the inverting output node is different from the logic value at the input node. The conductive path is positioned on one of the conductive layers, and is programmed for selectively connecting either one of the inverting output node or the non-inverting output node of the logic cell to an output terminal of the programmable stage.

Abstract: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

Abstract: A memory manufactured through a semiconductor process includes a substrate, a memory cell array formed on the substrate, a peripheral circuit formed on the substrate and electrically connected to the memory cell array for controlling access of the memory cell array, and a power distribution network formed substantially above the peripheral circuit or the memory cell array. The power distribution network is electrically connected to the peripheral circuit and the memory cell array for providing power to the peripheral circuit and the memory cell array.