Patents by Inventor Yung-Chien Huang

Yung-Chien Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230104442
    Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
  • Patent number: 11527622
    Abstract: A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20220223693
    Abstract: A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20110041646
    Abstract: A handlebar clamping device for a bicycle includes a handlebar, a mounting tube mounted on the handlebar and having a peripheral wall provided with two opposite mounting portions and two opposite openings located between the two mounting portions, and a clamping unit extending through the two openings of the mounting tube and pressing the handlebar to lock the mounting tube onto the handlebar. Thus, the handlebar clamping device only needs to provide a single clamping unit to lock the mounting tube onto the handlebar, thereby decreasing the cost of fabrication of the handlebar clamping device.
    Type: Application
    Filed: August 24, 2009
    Publication date: February 24, 2011
    Inventor: Yung-Chien Huang