Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Abstract: A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a dielectric material disposed over the substrate and the gate structure, a conductive structure extending within the dielectric material, and a void extending within the dielectric material and disposed over the gate structure.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

Abstract: A float switch device includes a tubular member, a magnet tube and a magnetic switch. The tubular member has a first restriction portion and a second restriction portion formed on an external surface thereof. The magnet tube is sleeved over the tubular member, and is movable between the first restriction portion and the second restriction portion. The magnetic switch includes at least two metal tongues, where each of the metal tongues includes an interior contact point and an exterior contact point. The float switch device is placed in a casing in such way that the exterior contact points are electrically connected to an external apparatus. When the casing is tilted upward or downward by the change in water level, the magnet tube moves between the first and second restriction portions to switch the float switch device between the ON/OFF state.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: A multi-band antenna mounted on a circuit board includes a ground plate perpendicularly connected to one side edge of the circuit board, a radiating plate perpendicularly connected to the other side edge of the circuit board, and a planar antenna element includes a high frequency radiating portion, a lower frequency radiating portion, a base plate, a capacitance portion and an inductance portion. The high frequency radiating portion and the lower frequency radiating portion are located at two ends of the circuit board, respectively, and both connected to the radiating plate. The base plate is connected to the radiating plate and located between the high and lower frequency radiating portions. The capacitance portion is parallel with the ground plate to form a capacitive coupling therebetween. The inductance portion is soldered to the ground plate. A simulation inductance is formed by the inductance portion.

Abstract: A wireless mouse includes a mouse housing, a printed circuit board assembly assembled in the mouse housing, and an antenna mounted on a front end of the printed circuit board assembly. The front end of the printed circuit board assembly defines two fastening holes spaced from each other along a direction perpendicular to a front-to-rear direction. The antenna has a substantial long-strip radiating portion. Two opposite ends of the radiating portion are bent rearward and then downward to form a hook portion and a feed portion which are respectively hooked in the corresponding fastening holes to make the radiating portion transversely mounted over the front end of the printed circuit board assembly. The feed portion is electrically connected with a feed circuit of the printed circuit board assembly.

Abstract: A wide-band antenna mounted on a circuit board includes a ground plate, a radiating plate perpendicularly connected to two side edges of the circuit board, and a planar antenna element which includes a base plate, an extending plate, and a ground portion. One side of the base plate defines a gap with a first coupling portion being formed, and a slot adjacent to the gap with a first strip being formed therebetween. A second strip is extended perpendicularly from the first strip. The extending plate is extended outward from one end of the base plate. The ground portion is extended outward from the second strip and connected to the ground plate. The first coupling portion and the ground portion have an interspace to form a capacitive coupling therebetween. A groove is formed among the first and second strips and the ground portion to form a simulation inductance thereamong.

Abstract: A wide-band antenna mounted on a circuit board includes a ground plate, a radiating plate perpendicularly connected to two side edges of the circuit board, and a planar antenna element which includes a base plate, an extending plate, and a ground portion. One side of the base plate defines a gap with a first coupling portion being formed, and a slot adjacent to the gap with a first strip being formed therebetween. A second strip is extended perpendicularly from the first strip. The extending plate is extended outward from one end of the base plate. The ground portion is extended outward from the second strip and connected to the ground plate. The first coupling portion and the ground portion have an interspace to form a capacitive coupling therebetween. A groove is formed among the first and second strips and the ground portion to form a simulation inductance thereamong.