Patents by Inventor Yung Chii Liang

Yung Chii Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power MOSFET having enhanced breakdown voltage
    Patent number: 6853033
    Abstract: A MOSFET includes a dielectric, preferably in the form of a metal thick oxide that extends alongside the MOSFET's drift region. A voltage across this dielectric between its opposing sides exerts an electric field into the drift region to modulate the drift region electric field distribution so as to increase the breakdown voltage of a reverse biased semiconductor junction between the drift region and body region. This allows for higher doping of the drift region, for a given breakdown voltage when compared to conventional MOSFETs.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: February 8, 2005
    Assignee: National University of Singapore
    Inventors: Yung Chii Liang, Ganesh Shankar Samudra, Kian Paau Gan, Xin Yang
  • Process for device using partial SOI
    Patent number: 6551937
    Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: April 22, 2003
    Assignees: Institute of Microelectronics, National University of Singapore
    Inventors: Cai Jun, Ren Chang Hong, Ranganathan Nagarajan, Narayanan Balasubramanian, Yung Chii Liang
  • Process for device using partial SOI
    Publication number: 20030040185
    Abstract: A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep tenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches.
    Type: Application
    Filed: August 23, 2001
    Publication date: February 27, 2003
    Applicant: Institute of Microelectronics
    Inventors: Cai Jun, Ren Chang Hong, Ranganathan Nagarajan, Narayanan Balasubramanian, Yung Chii Liang
  • Power MOSFET having enhanced breakdown voltage
    Publication number: 20030006453
    Abstract: A MOSFET includes a dielectric, preferably in the form of a metal thick oxide that extends alongside the MOSFET's drift region. A voltage across this dielectric between its opposing sides exerts an electric field into the drift region to modulate the drift region electric field distribution so as to increase the breakdown voltage of a reverse biased semiconductor junction between the drift region and body region. This allows for higher doping of the drift region, for a given breakdown voltage when compared to conventional MOSFETs.
    Type: Application
    Filed: June 4, 2002
    Publication date: January 9, 2003
    Inventors: Yung Chii Liang, Ganesh Shankar Samudra, Kian Paau Gan, Xin Yang