Patents by Inventor Yung-Ching Chao

Yung-Ching Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149485
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Application
    Filed: January 8, 2025
    Publication date: May 8, 2025
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Patent number: 12230595
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Publication number: 20240371915
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 12136644
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20230107187
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 6, 2023
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20230063726
    Abstract: An integrated circuit structure includes a semiconductor substrate, a passivation layer, a first protective layer, and a second protective layer. The passivation layer is over the semiconductor substrate. The first protective layer is over the passivation layer. The second protective layer is over the first protective layer, wherein a boundary of the first protective layer is confined within the second protective layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ching Chao, Wei-Han Chiang, Peng-Yuan Jung, Chin-Wei Kang, Cheng-Jen Lin
  • Patent number: 11532692
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20210288009
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Patent number: 11024593
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Cheng Jen Lin, Chin Wei Kang, Yu-Feng Chen, Mirng-Ji Lii
  • Publication number: 20210151550
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 10910466
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Kai Tzeng, Cheng Jen Lin, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20200127078
    Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
    Type: Application
    Filed: March 1, 2019
    Publication date: April 23, 2020
    Inventors: Chun Kai Tzeng, Lin Cheng Jen, Yung-Ching Chao, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20200105696
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 2, 2020
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Lin Cheng Jen, Kang Chin Wei, Yu-Feng Chen, Mirng-Ji Lii