Patents by Inventor Yung-ching Chen
Yung-ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126327Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
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Patent number: 11955154Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.Type: GrantFiled: May 16, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
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Patent number: 11942130Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.Type: GrantFiled: March 23, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jian-Jhong Chen, Yi-Ting Wu, Jen-Yu Wang, Cheng-Tung Huang, Po-Chun Yang, Yung-Ching Hsieh
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Patent number: 11804826Abstract: A semiconductor device includes a first functional block configured to provide a first predetermined function, a second functional block configured to provide a second predetermined function, a first capacitive device, a second capacitive device, a first coupling path, a first switch device and a second switch device. The first capacitive device is disposed physically proximate the first functional block. The second capacitive device is disposed physically proximate the second functional block. The first coupling path includes at least a first connection node connecting to the first functional block. The first switch device is controlled to selectively connect the first capacitive device to the first connection node. The second switch device is controlled to selectively connect the second capacitive device to the second functional block or a second connection node. The second connection node is disposed on the first coupling path and connecting to the first connection node.Type: GrantFiled: April 25, 2022Date of Patent: October 31, 2023Assignee: MediaTek Singapore Pte. Ltd.Inventors: Zhigang Duan, Yung-Ching Chen, Chang Liang, Jinghao Chen
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Publication number: 20230343719Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.Type: ApplicationFiled: June 23, 2023Publication date: October 26, 2023Inventors: Ru-Ying Huang, Yung-Ching Chen, Yueh-Chiou Lin, Yian-Liang Kuo
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Patent number: 11728279Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.Type: GrantFiled: January 12, 2022Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Ying Huang, Yung-Ching Chen, Yueh-Chiou Lin, Yian-Liang Kuo
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Publication number: 20220345113Abstract: A semiconductor device includes a first functional block configured to provide a first predetermined function, a second functional block configured to provide a second predetermined function, a first capacitive device, a second capacitive device, a first coupling path, a first switch device and a second switch device. The first capacitive device is disposed physically proximate the first functional block. The second capacitive device is disposed physically proximate the second functional block. The first coupling path includes at least a first connection node connecting to the first functional block. The first switch device is controlled to selectively connect the first capacitive device to the first connection node. The second switch device is controlled to selectively connect the second capacitive device to the second functional block or a second connection node. The second connection node is disposed on the first coupling path and connecting to the first connection node.Type: ApplicationFiled: April 25, 2022Publication date: October 27, 2022Applicant: MediaTek Singapore Pte. Ltd.Inventors: Zhigang Duan, Yung-Ching Chen, Chang Liang, Jinghao Chen
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Publication number: 20220139838Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.Type: ApplicationFiled: January 12, 2022Publication date: May 5, 2022Inventors: Ru-Ying Huang, Yung-Ching Chen, Yueh-Chiou Lin, Yian-Liang Kuo
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Patent number: 11227836Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.Type: GrantFiled: January 28, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Ying Huang, Yung-Ching Chen, Yueh-Chiou Lin, Yian-Liang Kuo
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Patent number: 11139281Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.Type: GrantFiled: June 6, 2016Date of Patent: October 5, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jung Wei Cheng, Tsung-Ding Wang, Ming-Da Cheng, Yung Ching Chen
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Publication number: 20210041889Abstract: A semantic map orientation device includes an image capturing device, a memory, and a processor. The memory stores map information, where the map information defines at least one zone in a space. The processor captures a semantic attribute list, where the semantic attribute list includes a plurality of object combinations and a plurality of spatial keywords, and the spatial keywords correspond to the object combinations respectively. The processor is configured to access the map information, control the image capturing device to capture image information corresponding to one of the at least one zone, and determine whether a plurality of objects captured in the image information matches one of the object combinations in the semantic attribute list. If the objects captured in the image information match the object combination, the processor classifies the zone into the spatial keyword corresponding to the object combination to update the map information.Type: ApplicationFiled: July 16, 2020Publication date: February 11, 2021Inventors: Yung-Ching CHEN, Kuang-Hsun HSIEH, Hsin-Chuan PAN
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Publication number: 20200126920Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.Type: ApplicationFiled: January 28, 2019Publication date: April 23, 2020Inventors: Ru-Ying Huang, Yung-Ching Chen, Yueh-Chiou Lin, Yian-Liang Kuo
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Patent number: 10090345Abstract: A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity.Type: GrantFiled: June 16, 2016Date of Patent: October 2, 2018Assignee: Taiwan SemIconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yung Ching Chen, Chien-Hsun Lee, Mirng-Ji Lii
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Patent number: 10020286Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint.Type: GrantFiled: October 16, 2015Date of Patent: July 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung Ching Chen, Chien-Hsun Lee, Chen-Hua Yu, Jiun Yi Wu, Ming-Da Cheng, Mirng-Ji Lii
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Patent number: 9768105Abstract: System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.Type: GrantFiled: April 20, 2012Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mirng-Ji Lii, Chen-Hua Yu, Chien-Hsiun Lee, Yung Ching Chen, Jiun Yi Wu
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Patent number: 9632516Abstract: A gas-supply system includes a gas container filled with gas, a gas flow controller coupled to the gas container, and an operation device electrically connected to the gas flow controller. The gas-supply system further includes a buffer tank coupled to the gas flow controller and configured to receive the gas from the gas container via the gas flow controller. Furthermore, a pressure transducer disposed on the buffer tank and configured to generate a pressure signal to the operation device according to the pressure of the gas in the buffer tank. The operation device is configured to generate a control signal to the gas flow controller according the pressure signal, and the gas flow controller is configured to adjust the flow rate of the gas according to the control signal to keep the pressure of the gas in the buffer tank in a predetermined pressure range.Type: GrantFiled: March 11, 2014Date of Patent: April 25, 2017Assignee: TAWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Yung-Long Chen, Chun-Feng Hsu, Heng-Yi Tseng, Chieh-Jan Huang, Chin-Hsing Su, Yung-Ching Chen
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Publication number: 20160300874Abstract: A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity.Type: ApplicationFiled: June 16, 2016Publication date: October 13, 2016Inventors: Chen-Hua Yu, Yung Ching Chen, Chien-Hsun Lee, Mirng-Ji Lii
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Publication number: 20160284676Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jung Wei Cheng, Tsung-Ding Wang, Ming-Da Cheng, Yung Ching Chen
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Patent number: 9397137Abstract: A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity.Type: GrantFiled: October 31, 2014Date of Patent: July 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Yung Ching Chen, Chien-Hsun Lee, Mirng-Ji Lii
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Patent number: RE49045Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a bump region and a tail region coupled to the bump region. The metal stud bumps are embedded in solder joints.Type: GrantFiled: August 7, 2017Date of Patent: April 19, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chien-Hsun Lee, Yung Ching Chen