Abstract: A thin film transistor is provided, and includes a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The first gate dielectric layer is disposed on the gate electrode and the substrate, and has a radio of the number of silicon-hydrogen bonds to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.2 and 1.0. The second gate dielectric layer is disposed on the first gate dielectric layer, and has a radio of the number of silicon-hydrogen bond to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.01 and 0.2. The channel layer is disposed on the second gate dielectric layer. The source electrode and drain electrode are disposed on the channel layer and located at two opposite sides of the channel layer.

Abstract: A thin film transistor is provided, and includes a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The first gate dielectric layer is disposed on the gate electrode and the substrate, and has a radio of the number of silicon-hydrogen bonds to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.2 and 1.0. The second gate dielectric layer is disposed on the first gate dielectric layer, and has a radio of the number of silicon-hydrogen bond to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.01 and 0.2. The channel layer is disposed on the second gate dielectric layer. The source electrode and drain electrode are disposed on the channel layer and located at two opposite sides of the channel layer.

Abstract: A method for adjusting a color lighting device, comprising the following steps: (a) selecting in a user interface to generate a control instruction having various colors with different mixing ratios; (b) transmitting the control instruction to the color lighting device, and storing the control instruction in a memory of the color lighting device; and (c) adjustably emitting color lighting according to the control instruction of step (b). The present invention provides the users the capability of adjusting the color lighting device, thereby furnishing atmosphere of enjoyment to the life of the users.

Abstract: A light-emitting diode (LED) device has a shade, an active heat-dissipation device and an LED module. The shade has a cavity. The active heat-dissipation device is mounted in the cavity in the shade and has a cooling board, an evaporator, a condenser, a compressor, an expansion valve and a refrigerant. The evaporator, condenser, compressor and expansion valve connect to each other to form a loop. The refrigerant is set in the loop. The LED module is mounted to the active heat-dissipation device and has at least one LED. The active heat-dissipation device dissipates the heat from the LED and even lowers the temperature of the LED under ambient temperature.

Abstract: A light-emitting diode (LED) device has a shade, an active heat-dissipation device and an LED module. The shade has a cavity. The active heat-dissipation device is mounted in the cavity in the shade and has a cooling board, an evaporator, a condenser, a compressor, an expansion valve and a refrigerant. The evaporator, condenser, compressor and expansion valve connect to each other to form a loop. The refrigerant is set in the loop. The LED module is mounted to the active heat-dissipation device and has at least one LED.

Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract: A method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.

Abstract: A method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.

Abstract: A method for forming a gate structure is provided. The forming method includes steps of providing a semiconductor substrate; forming an insulation layer, a first gate conductor layer, a second gate conductor layer, and a masking layer on the semiconductor substrate; removing portions of the masking layer, the semiconductor substrate, and the first gate conductor layer to define the gate structure by etching; executing a cleaning process to the semiconductor with a specific cleaning agent for etching the second gate conductor layer, thereby removing portions of the second gate conductor layer in the gate structure; and performing a thermal treatment process to the semiconductor substrate and forming an insulation spacer on the side surface of the gate structure.

Abstract: A method of forming a shallow trench in a specific region located between two adjacent deep trench capacitor constructions on a semiconductor substrate, each the deep trench capacitor construction having a collar construction and a conductor construction is provided. The method of forming a shallow trench includes steps of (a) defining a mask by forming a mask layer on the semiconductor substrate which has the deep trench capacitor constructions, (b) performing a first etching process with respect to the regions, which is not covered by the mask, so as to form a first depth trench, in which the first etching process has a relatively high selectivity ratio of the conductor construction relative to the mask, and (c) performing a second etching process with respect to the first depth trench so as to form a second depth trench, in which the second etching process has a selectivity ratio of the conductor construction relative to the collar construction substantially close to 1.