Abstract: An intelligent monitoring system for waste disposal and the method thereof are provided, which include a plurality of operational devices and stages. First, a transportation stage is performed to loading a transport vehicle with a waste so as to transport the waste to a disposal station for further treatment. A camera and a sensor for detecting abnormal conditions are installed any one of the operational devices or installed in the operational path of any one of the operational devices. The camera records the videos of the operational stages, captures the images from the videos and recognizes the images in order to determine whether the abnormal conditions occur in any one of the operational stages. Alternatively, the camera is triggered to capture the images and recognize the images after the abnormal conditions are detected by the sensor in order to determine whether the abnormal conditions actually occur.

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.

Abstract: Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.

Abstract: Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.

Abstract: Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.

Abstract: An MUT unit for testing memory modules includes a first circuit board; a second circuit board coupled to the first circuit board in a vertical orientation; a socket on a top surface of the first circuit board; and a resilient member electrically connecting the first and second circuit boards at an joint there between, wherein the resilient member comprises a horizontal segment that is welded to a bottom surface of the first circuit board, a vertical segment that is welded to a surface of the second circuit board, and a curved buffer segment connecting the horizontal segment and the vertical segment.

Abstract: An MUT unit for testing memory modules includes a first circuit board; a second circuit board coupled to the first circuit board in a vertical orientation; a socket on a top surface of the first circuit board; and a resilient member electrically connecting the first and second circuit boards at an joint there between, wherein the resilient member comprises a horizontal segment that is welded to a bottom surface of the first circuit board, a vertical segment that is welded to a surface of the second circuit board, and a curved buffer segment connecting the horizontal segment and the vertical segment.

Abstract: The test system for memory includes a controlling device, an address generating device, a data disturbing device and a comparing device. The controlling device is used for writing a first data into a memory. The address generating device is used for generating a plurality of first addresses and a plurality of second addresses corresponding to the memory. The data disturbing device is used for disturbing the first data using the first addresses to obtain a second data, and disturbing the second data using the second addresses to obtain a third data. The comparing device is used to for comparing the third data and the first data.