Patents by Inventor Yung Chong
Yung Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9790463Abstract: The disclosure provides a culturing medium for culturing a bacterium of genus Tepidimonas, including: a carbon source which is an organic acid, selected from a group consisting of acetate, lactate and butyrate; a nitrogen source selected from a group consisting of ammonium sulfate ((NH4)2SO4), ammonium nitrate (NH4NO3), ammonium chloride (NH4Cl) and urea; phosphate; magnesium chloride (MgCl2); yeast extract; and trace elements.Type: GrantFiled: March 28, 2014Date of Patent: October 17, 2017Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yin-Lung Han, Tai-Rong Guo, Jo-Shu Chang, Yung-Chong Lou, Chieh-Lun Cheng, Wan-Ju Yu, Chih-Hsi Liu
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Patent number: 9580738Abstract: The disclosure provides a method for producing extracellular proteins from genus Tepidimonas, including: performing a fermentation culturing to a bacteria of genus Tepidimonas with a culturing medium to form a fermented liquid, wherein the composition of the culturing medium includes a carbon source which is an organic acid, selected from a group consisting of acetate, lactate and butyrate; a nitrogen source selected from a group consisting of (NH4)2SO4, NH4NO3, NH4Cl and urea; phosphate; carbonate; MgCl2; yeast extract; and trace elements, and wherein the gas feeding rate for the fermentation culturing is about 0-0.1 vvm; and after the fermentation culturing is completed, collecting the fermented liquid, wherein the fermented liquid contains extracellular protein secreted from the bacteria of genus Tepidimonas.Type: GrantFiled: August 28, 2015Date of Patent: February 28, 2017Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yin-Lung Han, Jo-Shu Chang, Yung-Chong Lou, Chieh-Lun Cheng, Chih-Hsi Liu
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Publication number: 20160186226Abstract: The disclosure provides a method for producing extracellular proteins from genus Tepidimonas, including: performing a fermentation culturing to a bacteria of genus Tepidimonas with a culturing medium to form a fermented liquid, wherein the composition of the culturing medium includes a carbon source which is an organic acid, selected from a group consisting of acetate, lactate and butyrate; a nitrogen source selected from a group consisting of (NH4)2SO4, NH4NO3, NH4Cl and urea; phosphate; carbonate; MgCl2; yeast extract; and trace elements, and wherein the gas feeding rate for the fermentation culturing is about 0-0.1 vvm; and after the fermentation culturing is completed, collecting the fermented liquid, wherein the fermented liquid contains extracellular protein secreted from the bacteria of genus Tepidimonas.Type: ApplicationFiled: August 28, 2015Publication date: June 30, 2016Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yin-Lung HAN, Jo-Shu CHANG, Yung-Chong LOU, Chieh-Lun CHENG, Chih-Hsi LIU
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Publication number: 20150184121Abstract: The disclosure provides a culturing medium for culturing a bacterium of genus Tepidimonas, including: a carbon source which is an organic acid, selected from a group consisting of acetate, lactate and butyrate; a nitrogen source selected from a group consisting of ammonium sulfate ((NH4)2SO4), ammonium nitrate (NH4NO3), ammonium chloride (NH4Cl) and urea; phosphate; magnesium chloride (MgCl2); yeast extract; and trace elements.Type: ApplicationFiled: March 28, 2014Publication date: July 2, 2015Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yin-Lung HAN, Tai-Rong GUO, Jo-Shu CHANG, Yung-Chong LOU, Chieh-Lun CHENG, Wan-Ju YU, Chih-Hsi LIU
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Patent number: 8968687Abstract: A method for recycling metals is provided by using extracellular proteins excreted by a specific thermophilic bacteria strain, Tepidimonas fonticaldi sp. nov., in which the extracellular proteins show excellent metal-ion binding ability, being useful in recycling rare earth metal ions and precious metal ions from geothermal fluids, boiler solutions, industrial wastewater or hard water.Type: GrantFiled: December 30, 2013Date of Patent: March 3, 2015Assignee: Industrial Technology Research InstituteInventors: Yin-Lung Han, Tai-Rong Guo, Jo-Shu Chang, Yung-Chong Lou, Wan-Ju Yu
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Publication number: 20140193316Abstract: A method for recycling metals is provided by using extracellular proteins excreted by a specific thermophilic bacteria strain, Tepidimonas fonticaldi sp. nov., in which the extracellular proteins show excellent metal-ion binding ability, being useful in recycling rare earth metal ions and precious metal ions from geothermal fluids, boiler solutions, industrial wastewater or hard water.Type: ApplicationFiled: December 30, 2013Publication date: July 10, 2014Applicant: Industrial Technology Research InstituteInventors: Yin-Lung HAN, Tai-Rong GUO, Jo-Shu CHANG, Yung-Chong LOU, Wan-Ju YU
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Publication number: 20070278591Abstract: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.Type: ApplicationFiled: June 1, 2006Publication date: December 6, 2007Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Zhijiong Luo, Yung Chong, Kevin Dezfulian, Huilong Zhu, Judson Holt
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Publication number: 20070235802Abstract: An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.Type: ApplicationFiled: April 5, 2006Publication date: October 11, 2007Inventors: Yung Chong, Zhijiong Luo, Judson Holt
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Publication number: 20070205469Abstract: A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.Type: ApplicationFiled: March 6, 2006Publication date: September 6, 2007Applicants: Chartered Semiconductor Manufacturing Ltd., International Business Machines CorporationInventors: Yung Chong, Zhijiong Luo
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Publication number: 20070196996Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed over the stress-altering material.Type: ApplicationFiled: February 17, 2006Publication date: August 23, 2007Inventors: Jin-Ping Han, Yung Chong
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Publication number: 20070138570Abstract: A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor.Type: ApplicationFiled: December 16, 2005Publication date: June 21, 2007Inventors: Yung Chong, Zhijiong Luo, Joo Kim, Judson Holt
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Publication number: 20070132038Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses.Type: ApplicationFiled: December 8, 2005Publication date: June 14, 2007Inventors: Yung Chong, Zhijiong Luo, Joo Kim, Brian Greene, Kern Rim
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Publication number: 20070122955Abstract: There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.Type: ApplicationFiled: November 29, 2005Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhijiong Luo, Yung Chong, Huilong Zhu
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Publication number: 20070032026Abstract: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.Type: ApplicationFiled: August 2, 2005Publication date: February 8, 2007Inventors: Kuang Ong, Kin Pey, King Chui, Ganesh Samudra, Yee Yeo, Yung Chong
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Publication number: 20070020861Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.Type: ApplicationFiled: July 16, 2005Publication date: January 25, 2007Inventors: Yung Chong, Brian Greene, Siddhartha Panda, Nivo Rovedo
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Publication number: 20070020864Abstract: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.Type: ApplicationFiled: July 16, 2005Publication date: January 25, 2007Inventors: Yung Chong, Brian Greene
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Publication number: 20060160290Abstract: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface.Type: ApplicationFiled: January 20, 2005Publication date: July 20, 2006Inventors: Yung Chong, Dong Sohn, Chew-Hue Ang, Purakh Vermo, Liang Hsia
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Publication number: 20060160343Abstract: An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening.Type: ApplicationFiled: January 20, 2005Publication date: July 20, 2006Inventors: Yung Chong, Dong Sohn, Liang Hsia
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Publication number: 20060105533Abstract: The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate is provided. The substrate has a NMOS area and a PMOS area. We form a NMOS mask over the NMOS area. We form a first semiconductor layer over the PMOS area. We remove the mask. We form a second semiconductor layer over the NMOS area. Then we form an isolation region in the substrate between at least portions of the NMOS and the PMOS areas. We form PMOS devices in the PMOS area and form NMOS devices in the NMOS area.Type: ApplicationFiled: November 16, 2004Publication date: May 18, 2006Inventors: Yung Chong, Liang Hsia, Chew Ang