Abstract: A method includes etching a first trench in a semiconductor substrate to form a first fin and a second fin, and forming a shallow trench isolation (STI) region in the first trench, where forming the STI region includes depositing a first dielectric layer over top surfaces of the first fin and the second fin, and on sidewalls and a bottom surface of the first trench, the first dielectric layer including carbon, depositing a second dielectric layer over the first dielectric layer, and in the first trench, where the second dielectric layer fills the first trench, and performing an anneal process, where the anneal process releases carbon from the first dielectric layer into the second dielectric layer.

Abstract: A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.

Abstract: A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first/second set of signal traces is coupled with the first and third parts of the first/second set of signal traces. All the third parts are in the first signal layer and parallel.

Abstract: A shielding circuit applied to a semiconductor device includes a first shielding structure and a second shielding structure. The first shielding structure forms a first closed loop and is disposed adjacent to an inductor comprised in the semiconductor device. The second shielding structure forms a second closed loop and is disposed adjacent to an electronic component coupled to the inductor.

Abstract: A dental preparation block guide comprises a chamber that is customized to receive at least one tooth of a patient for a shape-optimized restoration of the at least one tooth; and a channel formed in a surface of the block guide at a location selected relative to the shape-optimized restoration to be performed, the channel comprising an aperture extending through the surface to the chamber such that a dental handpiece can be inserted into and guided within the channel while a tool of the dental handpiece can interact with the at least one tooth in the chamber through the aperture to form a shape-optimized preparation in the at least one tooth to receive the shape-optimized restoration. Related methods and system, as well as other devices, also are disclosed.

Abstract: A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.

Abstract: A multifunctional air pollution reduction device includes a tool and a multifunctional pollutant remover. The multifunctional pollutant remover is adjacent to or integrated with the tool. The multifunctional pollutant remover can not only reduce air pollution, but also help reduce one or more of the following problems when using the tools: noise, vibration and/or slip.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: Inductor-capacitor oscillators and common mode resonators are provided. The inductor-capacitor oscillator includes a first transistor, a second transistor, an inductor, a first capacitor, a second capacitor, a first winding, and a second winding. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal and a sixth terminal. The first, second and third terminals are electrically connected to the fifth, fourth and sixth terminals, respectively. The first capacitor and the inductor are coupled between the first terminal and the fourth terminal. The second capacitor is coupled between the third terminal and a reference voltage. The first winding is coupled between the third terminal and the reference voltage. The second winding is coupled between the third terminal and the reference voltage. The first winding and the second winding are symmetric to each other.

Abstract: Inductor-capacitor oscillators and common mode resonators are provided. The inductor-capacitor oscillator includes a first transistor, a second transistor, an inductor, a first capacitor, a second capacitor, a first winding, and a second winding. The first transistor has a first terminal, a second terminal, and a third terminal. The second transistor has a fourth terminal, a fifth terminal and a sixth terminal. The first, second and third terminals are electrically connected to the fifth, fourth and sixth terminals, respectively. The first capacitor and the inductor are coupled between the first terminal and the fourth terminal. The second capacitor is coupled between the third terminal and a reference voltage. The first winding is coupled between the third terminal and the reference voltage. The second winding is coupled between the third terminal and the reference voltage. The first winding and the second winding are symmetric to each other.

Abstract: Disclosed is a duty cycle corrector including a buffer circuit, an upper circuit, and a lower circuit. The buffer circuit includes: a first buffer circuit receiving a first input signal and thereby outputting a second output signal to a second output terminal; a second buffer circuit receiving a second input signal and thereby outputting a first output signal to a first output terminal; and a latch circuit coupled between the first and second output terminals. The upper circuit is coupled between a high voltage terminal and the buffer circuit and transmits current to the first and second output terminals according to each of the first and second input signals. The lower circuit is coupled between the buffer circuit and a low voltage terminal and withdraws current flowing through the first and second output terminals according to each of the first and second input signals.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A photosensitive dry film composition includes a hexaarylbiimidazole blend, a photosensitizer that absorbs in the 350 to 410 nm wavelength range and a hydrogen donor. The hexaarylbiimidazole blend includes a hexaarylbiimidazole having a molar extinction coefficient of at least 4,000 in the 350 to 410 nm wavelength range and a hexaarylbiimidazole having a molar extinction coefficient of less than 4,000 in the 350 to 410 nm wavelength range.