Abstract: A headphone includes a headgear and two earmuffs connected to opposite ends of the headgear, and each of the earmuffs includes an adjustment assembly. The adjustment assembly includes a base, two elastic members, two protrusions, and two sliding blocks. The base has two opposite accommodating parts and two guiding grooves. The elastic members are disposed in the accommodating parts, respectively, and the elastic members extend along a first axial direction. The protrusions are slidably connected to the guiding grooves, respectively, and protrude into the accommodating parts. The sliding blocks are disposed in the accommodating parts, respectively, and each of the sliding blocks is respectively connected between the corresponding protrusion and the corresponding elastic member.

Abstract: There is provided a structure to improve BSI global shutter efficiency. In a sensor pixel circuit, at least one strong electric field is formed at the position of a floating diffusion region to accordingly have the effect of shielding the floating diffusion region. Or, the semiconductor material from the floating diffusion node toward a light incident direction is removed in the manufacturing process such that a depletion region cannot be formed in this direction. Or, a reflection layer or a photoresist layer is formed in the light incident direction to block the light. In these ways, charges generated by the undesired noises are reduced, and noise charges are difficult to reach the floating diffusion region thereby improving the shutter efficiency.

Abstract: There is provided a structure to improve BSI global shutter efficiency. In a sensor pixel circuit, at least one strong electric field is formed at the position of a floating diffusion region to accordingly have the effect of shielding the floating diffusion region. Or, the semiconductor material from the floating diffusion node toward a light incident direction is removed in the manufacturing process such that a depletion region cannot be formed in this direction. Or, a reflection layer or a photoresist layer is formed in the light incident direction to block the light. In these ways, charges generated by the undesired noises are reduced, and noise charges are difficult to reach the floating diffusion region thereby improving the shutter efficiency.

Abstract: There is provided a structure to improve BSI global shutter efficiency. In a sensor pixel circuit, at least one strong electric field is formed at the position of a floating diffusion region to accordingly have the effect of shielding the floating diffusion region. Or, the semiconductor material from the floating diffusion node toward a light incident direction is removed in the manufacturing process such that a depletion region cannot be formed in this direction. Or, a reflection layer or a photoresist layer is formed in the light incident direction to block the light. In these ways, charges generated by the undesired noises are reduced, and noise charges are difficult to reach the floating diffusion region thereby improving the shutter efficiency.

Abstract: The present invention provides a global shutter high dynamic range pixel and a global shutter high dynamic range image sensor. The global shutter high dynamic range pixel includes: a photoelectric transducer unit, a floating node, a first charge transfer unit, a second charge transfer unit and a pixel signal output unit. The first charge transfer unit includes a Metal-Oxide-Semiconductor (MOS) capacitor. The MOS capacitor is configured to operably accumulate at least a portion of the charges transferred from the photoelectric transducer unit. The MOS capacitor is turned ON or OFF according to a control signal, thereby forming a gate-induced potential well internally within the MOS capacitor, so as to control the portion of charges.

Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract: In a method of manufacturing a NOR flash memory, two times of tilt ion implantation process are conducted to form a tilt-implanted source region, so as to improve the distribution of the source region in a semiconductor substrate and reduce the probability of short channel effect (SCE) between the drain regions and the source region in the NOR flash memory.

Abstract: A method for fabricating a NOR semiconductor memory structure includes: performing a deeply doped source ion implantation process and a lightly doped drain ion implantation process; forming oxide layer walls on two said sides of a gate structure, respectively; performing a pocket implant process with control of an incident angle thereof; and performing a deeply doped drain ion implantation process. Characteristics of the NOR semiconductor memory structure are improved by controllably changing the position of a pocket implant region.

Abstract: In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole.

Abstract: In a method of manufacturing a NOR flash memory, when the memory device dimensions are further reduced, the forming of spacers at two lateral sides of the gate structures is omitted, and a space between two gate structures can be directly filled up with a dielectric spacer or a shallow trench isolation (STI) layer. Therefore, it is possible to avoid the problem of increased difficulty in manufacturing memory device caused by forming spacers in an extremely small space between the gate structures. The method also enables omission of the self-alignment step needed to form the salicide layer. Therefore, the difficulty in self-alignment due to the extremely small space between the gate structures can also be avoided.

Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.

Abstract: A flash memory applied in NAND and/or NOR flash memory has a silicon-oxide-nitride-oxide-silicon cell structure, uses channel-hot-electron injection as a write mechanism thereof to have a localized trapping characteristic, and uses hot-hole injection as an erase mechanism thereof. The flash memory uses an oxide-nitride-oxide structure to replace a floating gate, and thereby solves the problem of an entire leakage caused by a local leakage of the floating gate. The flash memory may be miniaturized without the problem of data mutual interference, and may be easily integrated into the CMOS process to largely reduce the manufacturing cost thereof. Meanwhile, the flash memory also enables faster program time and erase time.

Abstract: The present invention provides a method for producing a shallow trench isolation, comprises: forming a plurality of first grooves on a silicon substrate with a mask etching method, wherein the silicon substrate comprises a silicon layer, an oxide layer and a first polysilicon layer; conducting oxidation process on an inner peripheral portion of the second grooves to form an insulting layer. The depth of the insulating layer on the periphery of the first polysilicon layer formed by the oxidation process is larger than the depths of the insulating layers that are formed on the silicon layer and on the oxidation layer through the oxidation process; filling high density plasma oxide layer into the second grooves to form a plurality of high density plasma oxide layer fillers; removing the first polysilicon layer by etching; covering the silicon substrate with a second polysilicon layer by deposition; and polishing the second polysilicon layer to form a plurality of self-aligned floating gate.

Abstract: A non-volatile memory is provided. At least two bit lines are disposed in a substrate. The two bit lines are arranged in parallel and extend in a first direction. A plurality of select gate structures is disposed on the substrate between the two bit lines respectively. The select gate structures are arranged in parallel and extend in a first direction. A gap is disposed between each two neighboring select gate structures. A plurality of control gate lines is disposed on the substrate and fills in the gaps between two neighboring select gate structures respectively. The control gate lines are arranged in parallel and extend in a second direction, which crosses the first direction. A plurality of charge storage layers is disposed between the select gate structures and control gate lines respectively.

Abstract: A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and the charge storage layers form a memory cell column. The two doped regions are disposed in the substrate at both sides of the memory cell column.

Abstract: A non-volatile memory unit includes a substrate, a conductive layer, a charge storage layer, a first doped regions, two second doped regions, a first bit line and a second bit line. Wherein, there is a trench in the substrate, the conductive layer is disposed in the substrate and filled the trench. The charge storage layer is disposed between the conductive layer and the substrate. The first doped region is disposed in the substrate below the trench, and the second doped regions are disposed in the substrate on the two sides of the trench respectively. Plural control gates are located above the select gates and aligned in parallel and extend in a second direction. The first bit line and the second bit line are disposed on the substrate and electrically connected to the two second doped regions respectively and parallel to each other.

Abstract: A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region and a p-base region, and a source contact metal layer. The p+ heavily doped region the n+ heavily doped region and the p-base region are abutting each other. The former two are extended to the front surface of the silicon carbide substrate having the source contact metal layer formed over and the latter one is beneath them. Moreover, the p-base region is separated from the trench by an accumulation channel. The drain contact metal layer is formed on the rear surface of the silicon carbide substrate where the rear region of the silicon carbide is heavily doped than the front region thereof.

Abstract: A structure of accumulated type trench MOSFET in silicon carbide(SiC) and forming method are disclosed. The MOSFET includes a trench gate having a gate oxide layer, a polysilicon layer, a source region, and a drain region. The source region contains a p+ heavily doped region, an n+ heavily doped region and a p-base region, and a source contact metal layer. The p+ heavily doped region the n+ heavily doped region and the p-base region are abutting each other. The former two are extended to the front surface of the silicon carbide substrate having the source contact metal layer formed over and the latter one is beneath them. Moreover, the p-base region is separated from the trench by an accumulation channel. The drain contact metal layer is formed on the rear surface of the silicon carbide substrate where the rear region of the silicon carbide is heavily doped than the front region thereof.