Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces the first data in cache with the second data read from the memory apparatus, the process issues the read second data request first, followed by the write-back first data request. The detector provides a detecting signal when the processor issues the read second data request and cancels the provided detecting signal when the processor issues the write-back first data request. Each pass-gate decides whether to pass the third access request outputting from each corresponding access-consumer and transmit it to the memory apparatus according to the detecting signal respectively.

Abstract: An interrupt coalescing scheme for high throughput TCP offload engine and method thereof are disclosed. An interrupt descriptor queue is used, that TCP offload engine saves TCP connection information and interrupt information in an interrupt event descriptor per interrupt. Meanwhile the software processes an interrupt by reading interrupt event descriptors asynchronously. The software may process multiple interrupt event descriptors in one interrupt context.

Abstract: High-speed networking application equipments with a layer-2 to layer-7 hardware search engine and method are with flexibility and performance improvement. The multi-layer switches/routers, network address translation (NAT) gateway, firewall/VPN router and network attached storage (NAS) may use the search engine for fast and efficient search requirement.

Abstract: A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces the first data in cache with the second data read from the memory apparatus, the process issues the read second data request first, followed by the write-back first data request. The detector provides a detecting signal when the processor issues the read second data request and cancels the provided detecting signal when the processor issues the write-back first data request. Each pass-gate decides whether to pass the third access request outputting from each corresponding access-consumer and transmit it to the memory apparatus according to the detecting signal respectively.