Patents by Inventor Yung-Chung Yao

Yung-Chung Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7803692
    Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: September 28, 2010
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
  • Publication number: 20100003796
    Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 7, 2010
    Applicant: POWERCHIP SEMICONDUCTOR CORP.
    Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
  • Patent number: 7612433
    Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: November 3, 2009
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
  • Publication number: 20060183295
    Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.
    Type: Application
    Filed: September 21, 2005
    Publication date: August 17, 2006
    Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao