Abstract: A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.

Abstract: A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.

Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.

Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: The method and circuit for testing a TSV of the present invention exploit the electronic property of the TSV under test. The TSV under test is first reset to a first state, and is then sensed at only one end to determine whether the TSV under test follows the behavior of a normal TSV, wherein the reset and sense steps are performed at only one end of the TSV under test. If the TSV under test does not follow the behavior of a normal TSV, the TSV under test is determined faulty.

Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.

Abstract: A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV.

Abstract: A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

Abstract: A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.

Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.

Abstract: A low-power reading reference circuit for split-gate flash memory includes at least a pair of first reference cell and a second reference cell, which provides a reading reference current to regular cells of the split-gate flash memory. A first floating gate of the first reference cell and a second floating gate of the second reference cell are connected to an output of a logic circuit. The logic circuit receives at least one external state signal to determine whether the split-gate flash memory is ready to switch to reading mode or not, and then switches the first floating gate and the second floating gate between the state of activated and deactivated, so as to activate the first reference cell or the second reference cell to provide the reference current.

Abstract: A comparable circuit employed for parallel testing DRAM devices is disclosed, wherein the disclosed comparable circuit basically encompasses a three-stage circuit composed of two XNOR gates, a XOR gate, and a tri-state output buffer. The first stage consisting of the XOR gate and a first XNOR gate parallel receive the stored test pattern from the detected memory cell to respectively generate a pair of first comparison results. A second exclusive XNOR gate included in the second stage receives the first comparison results, and connects with the third stage through an output terminal of the second XNOR gate. The third stage composed of the output buffer couples with the output terminal of the second XNOR gate to generate a second comparison result further routed to I/O bus. Chess-like test patterns can be employed in the disclosed comparable circuit due to two mutually exclusive logic gates are generated in the first stage.

Abstract: A static random access memory (SRAM) cell is formed by a tunnel switched diode (TSD) and a pair of transistors. The TSD has a characteristic I-V curve exhibiting a negative differential resistance region that allows the TSD to function as a bi-stable storage device. NMOS and PMOS transistors coupled between the TSD and word and bit lines function to access the TSD for purposes of address, read and write functions of the cell. The cells can be connected in high density, high performance arrays. The TSD's are formed from layered materials that result in small cell size while allowing for high level of cell current.

Abstract: A voltage clamping circuit prevents fluctuation in a cell plate biasing reference voltage applied to the commonly connected plates of cell capacitors of an array of memory storage cells of a DRAM. The voltage clamping circuit has a clamp signal terminal for receiving a clamping signal that enables the voltage clamping circuit The voltage clamping circuit further has a clamping circuit for providing additional current to the common plates of the cell capacitors of the DRAM array to maintain the plate bias voltage level at the common plates of the cell plate capacitor of the cell. The clamping circuit is has a first current sourcing circuit that is connected the plate bias voltage source for providing the additional current to the plate bias voltage source while maintaining plate bias voltage level when the voltage clamping circuit is enabled.

Abstract: A high-voltage switch circuit is disclosed, which includes at least one voltage source input terminal for providing at least one voltage source (HV1), and a passing circuit (T0) for controllably passing the voltage source. The present invention also includes a pumping circuit (202) for raising voltage level of one output terminal (C) thereof. At least one switch circuit (T6 or T7) under control of a switch signal is used so that the voltage source controllably propagates to one output terminal (OUT1, OUT2) of the switch circuit through the passing circuit. Finally, a circuit (T4) is used for forcing the output terminal of the pumping circuit and one internal node (A) of the pumping circuit to an equal potential, so that the voltage source propagates to the output terminal of the switch circuit through the forcing circuit when the output terminal of the switch circuit is coupled to a ground.

Abstract: A reference voltage generation circuit has a start-up circuit that will force the reference voltage generation circuit to assume a normal operation mode producing the desired reference voltage level and will reduce noise coupled from a power supply voltage source. The start-up circuit for reference voltage generation circuit will be disabled when a sensing circuit has determined that the reference voltage generation circuit has attained the desired reference voltage level.

Abstract: The present invention discloses a Schmitt-trigger circuit with less power consumption by reducing the amount of the required DC current. The Schmitt-trigger circuit disclosed in the present invention basically encompasses a comparison circuit, a first current cutting circuit, and a second current cutting circuit. The comparison circuit receives the input signal and then generates the output signal. Both the first and second current cutting circuits feed in the output signal, and then generate feedback signals to feed the comparison circuit for cutting the DC current path when the input signal rises or falls to predetermined trigger points. When there is only one of the first and second current cutting circuits is required, the higher or lower trigger point can be adjusted without necessary to vary the size-ratio of the PMOS and NMOS transistors.

Abstract: The present invention discloses a precharge circuit for preventing undesired output pulses caused by the current sensing circuit of the flash memory devices. The access time of the read-cycle also can be decreased after the undesired output pulses are completely removed. Basically, the circuit disclosed by the invention encompasses the current mirror and the cell array as conventionally; a control circuit, a voltage detector and a precharge circuit to remove the undesired output pulses. The control circuit couples with the current mirror, the voltage detector, and the precharge circuit. The current mirror is used to generate output waveform. The precharge circuit couples with the cell array with a bit line, and pre-charges the voltage level of the bit line to a predetermined expected value. The control circuit controls the precharge circuit to precharge the bit line when the read-cycle starts. Whole the current sensing circuit keeps disable until the voltage level of the bit line rises to an expected value.