Abstract: A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another.

Abstract: A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench.

Abstract: A substrate having thereon an epitaxial layer is provided. A hard mask having an opening is formed on the epitaxial layer. A sidewall spacer is formed within the opening. A first trench is etched into the epitaxial layer through the opening. A dopant source layer is formed on the surface of the first trench. The dopants are driven into the epitaxial layer to form a doped region within the first trench. The doped region includes a first region adjacent to the surface of the first trench and a second region farther from the surface. The entire dopant source layer and the spacer are removed. A sacrificial layer is then filled into the first trench. The sacrificial layer and the epitaxial layer within the first region are etched away to form a second trench.

Abstract: A method for fabricating a semiconductor transistor device. An epitaxial layer is grown on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A spacer is formed on a sidewall of the gate trench. A recess is formed at the bottom of the gate trench. A thermal oxidation process is performed to form an oxide layer in the recess. The oxide layer completely fills the recess. The spacer is then removed. A gate oxide layer is formed on the exposed sidewall of the gate trench. A gate is then formed into the gate trench.

Abstract: A method for fabricating a power semiconductor device is disclosed. A substrate having thereon a plurality of die regions and scribe lanes is provided. A first epitaxial layer is formed on the substrate. A hard mask is formed on the first epitaxial layer. A trench is etched into the first epitaxial layer through an opening in the hard mask. The opening and the trench both traverse the die regions and scribe lanes in their longitudinal direction. The hard mask is then removed. A second epitaxial layer is formed in the trench. After polishing the second epitaxial layer, a third epitaxial layer is formed to cover the first and second epitaxial layers.

Abstract: A method of fabricating a super junction transistor is provided. A drain substrate is provided. An epitaxial layer is formed on the drain substrate. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed.

Abstract: The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type.

Abstract: A method of fabricating a super junction transistor is provided. A drain substrate is provided. An epitaxial layer is formed on the drain substrate. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed.

Abstract: A method for fabricating a trench type transistor. An epitaxial layer is provided on a semiconductor substrate. A hard mask with an opening is formed on the epitaxial layer. A gate trench is etched into the substrate through the opening. A gate oxide layer and a trench gate are formed within the gate trench. After forming a cap layer atop the trench gate, the hard mask is removed. An ion well and a source doping region are formed in the epitaxial layer. A spacer is then formed on a sidewall of the trench gate and the cap layer. Using the cap layer and the spacer as an etching hard mask, the epitaxial layer is etched in a self-aligned manner, thereby forming a contact hole.

Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.

Abstract: The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench.

Abstract: A super junction transistor includes a drain substrate, an epitaxial layer, wherein the epitaxial layer is disposed on the drain substrate, a plurality of gate structure units embedded on the surface of the epitaxial layer, a plurality of trenches disposed in the epitaxial layer between the drain substrate and the gate structure units, a buffer layer in direct contact with the inner surface of the trenches, a plurality of body diffusion regions with a first conductivity type adjacent to the outer surface of the trenches, wherein there is at least a PN junction on the interface between the body diffusion region and the epitaxial layer, and a doped source region, wherein the doped source region is disposed in the epitaxial layer and is adjacent to the gate structure unit.

Abstract: A semiconductor power device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth deeper than the junction depth in the ion well; a gate oxide layer in the gate trench; a gate embedded the gate trench; and a pocket doping region in the epitaxial layer. The pocket doping region is adjacent to and covers at least a corner of the gate trench.

Abstract: A semiconductor transistor device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth shallower than the junction depth in the ion well; a recess at the bottom of the gate trench; a gate oxide layer at surface of the gate trench and in the recess to form a protruding tip structure; a gate in the gate trench; and a drain extension region between the gate trench and the epitaxial layer.

Abstract: A semiconductor transistor device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth shallower than the junction depth in the ion well; a recess at the bottom of the gate trench; a gate oxide layer at surface of the gate trench and in the recess to form a protruding tip structure; a gate in the gate trench; and a drain extension region between the gate trench and the epitaxial layer.

Abstract: The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.

Abstract: A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench.

Abstract: A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided. An opening is formed in the hard mask. The substrate is etched through the opening to thereby form a first trench. A spacer is formed on a sidewall of the first trench. A second trench is then etched into the substrate through the first trench by using the spacer as an etching hard mask. The substrate within the second trench is then oxidized by using the spacer as an oxidation protection layer, thereby forming an oxide layer that fills the second trench. The spacer is then removed to reveal the sidewall of the first trench. A liner layer is then formed on the revealed sidewall of the first trench. A chemical vapor deposition process is then performed to deposit a dielectric layer that fills the first trench.

Abstract: An LED lamp for car use can be mounted in a long strip-shaped installation position, comprises a case, a light-reflecting base, a light source series and a lens base. The case is mounted corresponding to the installation position and the case has an opening and a first fixing part mounted opposite to the opening for being connected securely to the light-reflecting base. The light-reflecting base has a plurality of reflectors. Each of the reflectors has a second fixing part for being connected securely to the light source series. The light source series has a plurality of first LED lights and a plurality of second LED lights. The lens base located at the opening wraps the opening. The LED lamp for car use of the present invention can be used as a fog light or a daytime running light, and save space for installation of lamps in a car.

Abstract: A method for fabricating a semiconductor transistor device. An epitaxial layer is grown on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A spacer is formed on a sidewall of the gate trench. A recess is formed at the bottom of the gate trench. A thermal oxidation process is performed to form an oxide layer in the recess. The oxide layer completely fills the recess. The spacer is then removed. A gate oxide layer is formed on the exposed sidewall of the gate trench. A gate is then formed into the gate trench.